參數(shù)資料
型號(hào)： CMOD232+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 0K
描述： EVAL SYSTEM FOR MAX9850
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
Slave modes of operation allow the MAX9850 to operate
in any audio system where the LRCLK and BCLK must be
supplied from an external source. When operating in
slave mode, the MCLK supplied to the MAX9850 may be
either synchronous or asynchronous with LRCLK. Use the
slave integer mode if ICLK is synchronous and has an
integer multiple of 16 x LRCLK. Integer mode ensures
that the highest levels of full-scale-input signal perfor-
mance can be achieved. Slave noninteger mode offers
the highest degree of clock flexibility. ICLK does not
need to be synchronous or an integer multiple of
LRCLK when operating in slave noninteger mode.
Master modes of operation allow the MAX9850 to gener-
ate and supply an LRCLK and BCLK to other elements in
the system. Use master integer mode if the provided
ICLK is an integer multiple of 16 x LRCLK. Integer mode
ensures that the highest levels of full-scale input signal
performance can be achieved. Master noninteger mode
allows the MAX9850 to supply virtually any frequency
LRCLK with an accuracy better than ±0.5%.
The slave noninteger mode provides maximum flexibility
for ICLK and LRCLK frequencies. The ICLK and LRCLK
can be asynchronous and noninteger related. Connect
any available system clock that is listed on Table 5 in
the Internal Timing section. In slave noninteger mode,
the acceptable MCLK frequency range is the same as
master mode.
Master Integer Mode (MAS = 1, IM = 1)
The MAX9850 generates the LRCLK and BCLK in mas-
ter mode. LRCLK is an integer factor of ICLK by the fol-
lowing equation:
where:
fICLK = ICLK frequency. fICLK must be at least 160 x
fLRCLK for proper DAC operation.
NLSB = decimal value of the data contained in LSB(7:0)
(register 0x9, bits B7–B0).
fLRCLK = LRCLK frequency.
For example:
fICLK = 12.228MHz and NLSB = 16 (0x10), fLRCLK =
48kHz.
Solve the above equation for NLSB. Use master integer
mode if NLSB is an integer. Use master noninteger
mode if NLSB is not an integer.
Slave Integer Mode (MAS = 0, IM = 1)
The MAX9850 accepts LRCLK and BCLK from an
external digital audio source when in slave integer
mode. LRCLK must be an exact integer multiple of
ICLK to ensure proper operation. Program LSB(7:0)
(register 0x9, bits B7–B0) with the LRCLK division ratio.
Use the following equation to find the value that needs
to be programmed to LSB(7:0):
where:
fICLK = ICLK frequency. fICLK must be 160 x fLRCLK for
proper DAC operation.
fLRCLK = supplied LRCLK frequency.
NLSB = decimal value of the data contained in LSB(7:0)
(register 0x9, bits B7–B0).
For example:
fICLK = 11.2896MHz and fLRCLK = 44.1kHz, NLSB = 16
(0x10).
Solve the above equation for NLSB. Use slave integer
mode if NLSB is an integer. Use slave noninteger mode
if NLSB is not an integer.
Slave Noninteger (MAS = 0, IM = 0)
In slave noninteger mode, the MAX9850 accepts an
external LRCLK and converts the digital audio signal
using any asynchronous ICLK within the acceptable
operating range. The MAX9850 uses internal clock
recovery circuitry to generate all required internal clocks.
This allows the MAX9850 to operate in systems that do
not have dedicated clock sources or crystal oscillators.
Virtually any existing system clock will work. fICLK must
be at least 176 x fLRCLK for proper operation.
Master Noninteger Mode (MAS = 1, IM = 0)
The ICLK frequency in some applications may not be
an integer multiple of the desired LRCLK frequency.
The MAX9850, operating in master noninteger mode,
can generate and output any LRCLK frequency
between 8kHz to 48kHz (
±0.5%) with any ICLK frequen-
cy within the acceptable operating range. In this mode,
the MAX9850 generates LRCLK by dividing MCLK by
the ratio programmed into MSB(14:8) and LSB(7:0)
(register 0x8, bits B7–B0 and register 0x9, bits B6–B0).
The LRCLK sample frequency can have any noninteger
relationship with respect to MCLK. Calculate the values
for MSB(14:8) and LSB(7:0) with the following equation:
N
ROUND
f
MSB LSB
LRCLK
ICLK
,
=
×
2
22
N
f
LSB
ICLK
LRCLK
=
×
16
f
N
LRCLK
ICLK
LSB
=
×
16
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________
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