參數(shù)資料
型號: CR16HCS9VJE7Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 102/157頁
文件大小: 1256K
代理商: CR16HCS9VJE7Y
www.national.com
102
20.7
CR16CAN has access to one interrupt vector in the CR16
CPU. The interrupt process can be initiated from the follow-
ing sources.
CAN data transfer
— Reception of a valid data frame in the buffer. (Buffer
state changes from RX_READY to RX_FULL or
RX_OVERRUN).
— Successful transmission of a data frame. (Buffer state
changes from TX_ONCE to TX_NOT_ACTIVE or
RX_READY)
INTERRUPTS
— Successful response to a remote frame. (Buffer state
changes from TX_ONCE_RTR to TX_RTR).
— Transmit scheduling. (Buffer state changes from
TX_RTR to TX_ONCE_RTR).
CAN error conditions is the detection of an CAN error.
(The CEIPND bit in the CIPND register will be set as well
as the corresponding bits in the error diagnostic register
CEDIAG).
The receive/transmit interrupt access to every message buff-
er can be individually enabled/disabled in the CIEN register.
The pending flags of the message buffer are located in the
Figure 66.
Transmit Buffer States
TX_ONCE
1100
TX_NOT_ACTIVE
1000
RX_READY
0010
TX done
transmit
CPU writes 1000
Remote transmission
request sent - now wait
to receive a data frame
TX_RTR
1010
RTR
received
CPU writes 1010
transmit failed
CAN
schedules TX
TX_BUSY0
1101
TX_ONCE_RTR
1110
TX_BUSY2
1111
TX done
CAN
schedules TX
transmit
request cancelled
CPU writes 1000
transmit failed
CPU writes 1100
TX request
TX request
CPU writes 1110
*1
*1: TX request delayed
by a TX request of higher
priority message
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