參數(shù)資料
型號(hào): CR16HCS9VJE7Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 7/157頁
文件大?。?/td> 1256K
代理商: CR16HCS9VJE7Y
7
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conform to MICROWIRE or Serial Peripheral Interface (SPI)
specifications. It supports 8-bit and 16-bit data transfers.
The MICROWIRE interface allows several devices to com-
municate over a single system consisting of four wires: serial
in, serial out, shift clock, and slave enable. At any given time,
the MICROWIRE interface operates as the master or a slave.
The support supports the full set of slave select for multi-
slave implementation.
In master mode, the shift clock is generated on chip under
software control. In slave mode, a wake-up out of power-
save mode is triggered via the Multi-Input Wake-Up module.
3.14
The CR16CAN device contains a FullCAN class, CAN serial
bus interface for applications that require a high speed (up to
1MBits per second) or a low speed interface with CAN bus
master capability. The data transfer between CAN and the
CPU is established by 15 memory mapped message buffers,
which can be individually configured as receive or transmit
buffers. An incoming message is filtered by two masks, one
for the first 14 message buffers and another one for the 15th
message buffer to provide a basic CAN path. A priority de-
coder allows any buffer to have the highest or lowest transmit
priority. Remote transmission requests can be processed au-
tomatically by automatic reconfiguration to a receiver after
transmission or by automated transmit scheduling upon re-
ception. In addition, a time stamp counter (16-bits wide) is
provided to support real time applications.
The CR16CAN device is a fast core bus peripheral, which al-
lows single cycle byte or word read/write access. A set of di-
agnostic features (such as loopback, listen only, and error
identification) support the development with the CR16CAN
module and provide a sophisticated error management tool.
The CR16CAN receiver can trigger a wake-up condition out
of the power-save modes via the Multi-Input Wake-Up mod-
ule.
CR16CAN
3.15
The ACCESS.bus interface module (ACB) is a two-wire seri-
al interface with the ACCESS.bus physical layer. It is also
compatible with Intel’s System Management Bus (SMBus)
and Philips’ I
2
C bus. The ACB module can be configured as
a bus master or slave, and can maintain bi-directional com-
munications with both multiple master and slave devices.
The ACCESS.bus receiver can trigger a wake-up condition
out of the power-save modes via the Multi-Input Wake-Up
module.
ACCESS.BUS INTERFACE
3.16
The A/D Converter (ADC) module is a 12-channel multi-
plexed-input analog-to-digital converter. The A/D Converter
receives an analog voltage signal on an input pin and con-
verts the analog signal into an 8-bit digital value using suc-
cessive approximation. The CPU can then read the result
from a memory-mapped register. The module supports four
automated operating modes, providing single-channel or 4-
channel operation in single or continuous mode.
The device has a separate pin, Vref, for the A/D reference
voltage.
A/D CONVERTER
3.17
The Dual Analog Comparator (ACMP2) module contains two
independent analog comparators with all necessary control
logic. Each comparator unit compares the analog input volt-
ages applied to two input pins and determines which voltage
is higher. The CPU uses a memory-mapped register to con-
trol the comparator and to obtain the comparison results. The
comparison result can also be applied to comparator output
pins.
ANALOG COMPARATORS
3.18
A powerful cross-development tool set is available from Na-
tional Semiconductor and third parties to support the devel-
opment and debugging of application software for the
CR16MCS9. The tool set lets you program the application
software in C and is designed to take full advantage of the
CompactRISC architecture.
There are In-System Emulation (ISE) devices available for
the device from iSYSTEM, as well as lower-cost evaluation
boards. See your National Semiconductor sales representa-
tive for current information on availability and features of em-
ulation equipment and evaluation boards.
DEVELOPMENT SUPPORT
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