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self as no instruction or data can be fetched from it while it is
being programmed. All program and erase operations must
be preceded immediately by writing the proper key to the pro-
gram memory key register PGMKEY.
The flash EEPROM program memory is divided into 256 pag-
es, each page containing 64 words (each 16 bits wide). Each
page is further divided into two adjacent rows. A page erase
will erase one page. Programming is done by writing to all the
words within a row, one word following another sequentially
within one single high voltage pulse. This is supported
through a double-buffered write-data buffer scheme. Byte
programming is not supported. Programming should be done
on erased rows.
A mass erase requires the following code sequence (assum-
ing that this sequence will not be interrupted to do another
flash erase or programming):
1. Check for MSTAT.PGMBUSY not set.
2. Set up flash timing reload registers for mass erase oper-
ation.
3. Set FLCSR.MERASE = 1.
4. If interrupt was enabled, disable interrupt.
5. Write proper key value to PGMKEY.
6. Write to any valid location within the flash EEPROM pro-
gram memory.
7. If interrupt was disabled in step 4, re-enable interrupt.
8. Wait for MSTAT.PGMBUSY to clear.
9. Set FLCSR.MERASE = 0.
10. Restore flash timing reload registers for normal opera-
tion.
A page erase requires the following code sequence (assum-
ing that this sequence will not be interrupted to do another
flash erase or programming):
1. Check for MSTAT.PGMBUSY not set.
2. Set FLCSR.ERASE = 1.
3. If interrupt was enabled, disable interrupt.
4. Write proper key value to PGMKEY.
5. Write to any valid location within the page to be erased.
6. If interrupt was disabled in step 3, re-enable interrupt.
7. Set FLCSR.ERASE = 0.
When programming, the data to be written into the flash EE-
PROM program memory is first written into a double-buffered
write-data buffer. When a piece of data is written to the page
while the flash EEPROM program memory is idle, the write
cycle will start. Due to the double-buffered nature of the write-
data buffer, a second word can be written to the flash EE-
PROM program memory. This will then set FLCSR.PML-
FULL flag indicating the buffer is now full. When the first write
is done, the memory address would be incremented, and the
second word would be written to that address while keeping
the high voltage pulse active; the FLCSR.PMLFULL flag is
cleared. Another word can then be written to the buffer, and
this programming will repeat until there are no more words to
be programmed. This allows pipelined writes to different
words on the same row within the same high voltage pulse.
If the programming sequence exceeds a row, the flash pro-
gramming interface will automatically initiate a programming
pulse for the next row. The FLCSR.PMLFULL
bit is also
cleared when programming of the last word of the current
row is completed, e.g. programming of the entire row is com-
pleted and MSTAT.PGMBUSY is cleared. This means, the
separation of the program memory into rows is transparent to
the user, as the transition is handled by the flash program
memory interface. Figure 3 shows a flowchart for a program-
ming sequence.
9.1.5
The internal hardware of the device handles the timing of
erase and programming operations. To drive the timing con-
trol circuits, the device divides the system clock by a pro-
grammable prescaler factor. You should select a prescaler
value to produce a program/erase clock of 200 kHz (or as
close as possible to 200 kHz without exceeding 200 kHz).
For the timing control circuit to operate correctly, you must
Erase and Programming Timing
start
MSTAT.PGMBUSY
=1
disable interrupt
if necessary
write PGMKEY
re-enable interrupt
if necessary
write memory
last word
done
Yes
No
Yes
Yes
FLCSR.PMLFULL
=0
No
No
Figure 2.
Programming Sequence for
the Program Memory