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參數(shù)資料
| 型號： | CS4202-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 25/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO '97 48-TQFP |
| 標準包裝： | 2,000 |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 90 / 90 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（9x9） |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC3001
August 2004
31
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Alarms and Warning Flags
There are twenty different conditions that will cause the
MIC3001 to set one of the bits in the WARNx or ALARMx
registers. These conditions are listed in Table 19. The
less critical of these events generate warning flags by
setting a bit in WARN0 or WARN1. The more critical
events cause bits to be set in ALARM0 or ALARM1.
An event occurs when any alarm or warning condition
becomes true. Each event causes its corresponding
status bit in ALARM0, ALARM1, WARN0, or WARN1 to
be set. This action cannot be masked by the host. The
status bit will remain set until the host reads that particular
status register, a power on-off cycle occurs, or the host
toggles TXDISABLE.
If TXDISABLE is asserted at any time during normal
operation, A/D conversions continue. The A/D results for
all parameters will continue to be reported. All events will
be reported in the normal way. If they have not already
been individually cleared by read operations, when
TXDISABLE is de-asserted, all status registers will be
cleared.
Control and Status I/O
The logic for the transceiver control and status I/O is shown
schematically in Figure 14. Note that the internal drivers on
RXLOS, RATE_SELECT, and TXFAULT are all open-drain.
These signals may be driven either by the internal logic or
external drivers connected to the corresponding MIC3001
pins. In any case, the signal level appearing at the pins of
the MIC3001 will be reported in the control register status
bits.
Note
that
the
control
bits
for
TX_DISABLE
and
RATE_SELECT and the status bits for TXFAULT and
RXLOS do not meet the timing requirements specified in the
SFP MSA or the GBIC Specification, revision 5.5 (SFF-
8053) for the hardware signals. The speed of the serial
interface limits the rate at which these functions can be
manipulated and/or reported. The response time for the
control
and
status
bits
is
given
in
the
“Electrical
Characteristics” section.
Event
Condition
MIC3001 Response
Temperature high alarm
TEMP > TMAX
Set ALARM0[7]
Temperature low alarm
TEMP < TMIN
Set ALARM0[6]
Voltage high alarm
VIN > VMAX
Set ALARM0[5]
Voltage low alarm
VIN < VMIN
Set ALARM0[4]
TX bias high alarm
IBIAS > IBMAX
Set ALARM0[3]
TX bias low alarm
IBIAS < IBMIN
Set ALARM0[2]
TX power high alarm
TXOP > TXMAX
Set ALARM0[1]
TX power low alarm
TXOP < TXMIN
Set ALARM0[0]
RX power high alarm
RXOP > RXMAX
Set ALARM1[7]
RX power low alarm
RXOP < RXMIN
Set ALARM1[6]
Temperature high warning
TEMP > THIGH
Set WARN0[7]
Temperature low warning
TEMP < TLOW
Set WARN0[6]
Voltage high warning
VIN > VHIGH
Set WARN0[5]
Voltage low warning
VIN < VLOW
Set WARN0[4]
TX bias high warning
IBIAS > IBHIGH
Set WARN0[3]
TX bias low warning
IBIAS < IBLOW
Set WARN0[2]
TX power high warning
TXOP > TXHIGH
Set WARN0[1]
TX power low warning
TXOP < TXLOW
Set WARN0[0]
RX power high warning
RXOP > RXHIGH
Set WARN1[7]
RX power low warning
RXOP < RXLOW
Set WARN1[6]
Temperature high alarm
TEMP > TMAX
Set ALARM0[7]
Table 19. MIC3001 Events
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