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參數(shù)資料
| 型號(hào)： | CS4202-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 30/66頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO '97 48-TQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 90 / 90 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（9x9） |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC3001
August 2004
36
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Serial Port Operation
The MIC3001 uses standard Write_Byte, Read_Byte, and
Read_Word operations for communication with its host. It
also
supports
Page_Write
and
Sequential_Read
transactions. The Write_Byte operation involves sending
the device’s slave address (with the R/W bit low to signal
a write operation), followed by the address of the register
to be operated upon and the data byte. The Read_Byte
operation is a composite write and read operation: the
host first sends the device’s slave address followed by the
register address, as in a write operation. A new start bit
must then be sent to the MIC3001, followed by a repeat of
the slave address with the R/W bit (LSB) set to the high
(read) state. The data to be read from the part may then
be clocked out. A Read_Word is similar, but two
successive data bytes are clocked out rather than one.
These protocols are shown in Figure 22 to 25.
The MIC3001 will respond to up to four sequential slave
addresses depending on whether it is in OEM or User
mode. A match between one of the MIC3001’s addresses
and the address specified in the serial bit stream must be
made to initiate communication. The MIC3001 responds
to slave addresses A0h and A2h in User Mode; it also
responds to A4h and A6h in OEM Mode (assuming
I2CADR = Axh).
Page Writes
To increase the speed of multi-byte writes, the MIC3001
allows up to four consecutive bytes (one page) to be written
before the internal write cycle begins.
The entire non-
volatile memory array is organized into four-byte pages.
Each page begins on a register address boundary where
the last two bits of the address are 00b. Thus the page is
composed of any four consecutive bytes having the
addresses
xxxxxx00b,
xxxxxx01b,
xxxxxx10b,
and
xxxxxx11b.
The page write sequence begins just like a Write_Byte
operation with the host sending the slave address, R/W bit
low, register address, etc. After the first byte is sent the host
should receive an acknowledge. Up to three more bytes can
be sent in sequence. The MIC3001 will acknowledge each
one
and
increment
its
internal
address
register
in
anticipation of the next byte. After the last byte is sent, the
host issues a STOP. The MIC3001’s internal write process
then begins. If more than four bytes are sent, the MIC3001’s
internal address counter wraps around to the beginning of
the four-byte page.
To accelerate calibration and testing, NVRAM write cycles
can be disabled completely by setting the WRINH bit in
OEMCAL0. Writes to registers that do not have NVRAM
backup will not incur write-cycle delays when writes are
inhibited. Write operations on registers that exist only in
NVRAM will still incur write cycle delays.
Figure 22. Write Byte Protocol
Figure 23. Read Byte Protocol
Figure 24. Read_Word Protocol
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| CS4205-KQ | 功能描述:接口—CODEC IC AC’97 Codec for Docking Stations RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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