參數(shù)資料
型號(hào)： CS4202-JQZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 54/66頁(yè)
文件大?。?/td> 0K
描述： IC CODEC AUDIO '97 48-TQFP
標(biāo)準(zhǔn)包裝： 2,000
類(lèi)型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 90 / 90
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（9x9）
包裝： 帶卷 (TR)
Micrel, Inc.
MIC3001
August 2004
58
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Bit(s)
Function
Operation
D[7]
INV
Inverts the APC op-amp inputs.
When set to “0” the BIAS DAC
output is connected to the “+”input
and FB is connected to the “–” input
of the op amp. Set to “0” to use the
ADC feedback loop.
0 = emitter follower (no inversion);
1 = common emitter (inverted); read/write; non-volatile.
D[6]
GAIN
Sets the feedback voltage range by
changing the APCDAC output
swing; 0-V
REF
for optical feedback,
0-V
REF
/4 for electrical feedback.
1 = VREF/4 full scale;
0 = VREF full scale; read/write; non-volatile.
D[5]
BIASREF
Selects whether FB and VMPD are
referenced to ground or V
DD
and
selects feedback resistor termination
voltage (V
DDA
or GNDA).
1 = VDD; 0 = GND; read/write; non-volatile.
D[4:2]
RFB[2:0]
Selects internal feedback resistance.
(Resistors will be terminated to VDDA
or GNDA according to BIASREF.)
000 =
∞;
001 = 800
,
010 = 1.6k
,
011 = 3.2k
,
100 = 6.4k
,
101 = 12.8k
,
110 = 25.6k
,
111 = 51.2k
;
read/write; non-volatile.
D[1]
SRCE
V
BIAS
source vs. sink drive.
1 = source (NPN),
0 = sink (PNP); read/write; non-volatile.
D[0]
SPOL
Polarity of shutdown output, SHDN,
when active.
1 = high;
0 = low; read/write; non-volatile.
OEM Configuration Register 2 (OEMCFG2)
D[7]
I2CADR[3]
read/write
D[6]
I2CADR[2]
read/write
D[5]
I2CADR[1]
read/write
D[4]
I2CADR[0]
read/write
D[3]
LUTOFF
read/write
D[2]
LUTOFF
read/write
D[1]
LUTOFF
read/write
D[0]
LUTOFF
read/write
Default Value
1010 xxxxb = xxh (slave address = 1010xxxb)
Serial Address
A6h = 1010011b
Byte Address
2 = 02h
CAUTION: Changes to I2CADR take effect immediately! Any accesses following a write to I2CADR must be to the newly
programmed serial bus address. A valid OEM password is required for access to this register. This register is non-volatile and
will be maintained through power and reset cycles.
Bit(s)
Function
Operation
D[7:4]
I2CADR[3:0]
Upper four MSBs of the serial bus
slave address; writes take effect
immediately.
Read/write; non-volatile.
D[3:0]
LUTOFF
LUT offset. LUTOFF is added to the
result of the digital temperature
sensor to derive the table
index; writes take effect after reset.
Read/write; non-volatile.
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