參數(shù)資料
型號: CS4207-CNZ
廠商: Cirrus Logic Inc
文件頁數(shù): 21/77頁
文件大?。?/td> 0K
描述: IC CODEC AUD HDPN AMP COMM 48QFN
標(biāo)準(zhǔn)包裝: 429
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 3
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 105 / 110
電壓 - 電源,模擬: 2.97 V ~ 5.25 V
電壓 - 電源,數(shù)字: 2.97 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-QFN
供應(yīng)商設(shè)備封裝: 48-QFN-EP(6x6)
包裝: 托盤
其它名稱: 598-1796
28
DS880F4
CS4207
4.6
Power State Settings Reset (PS-SettingsReset)
PS-SettingsReset is reported as set to one ‘1’b when, during any low power state transition the settings that
were changed from the defaults (either through software or hardware) have been reset back to their default
state. When these settings have not been reset, this is reported as ‘0’b. The conditions that may reset set-
tings to their defaults are:
1.
Power On; always sets the PS-SettingsReset to ‘1’b for all widgets that report EPSS set to ‘1’b and that
have host programmable settings and reset all settings.
2.
Double Function Group Reset: sets PS-SettingsReset to ‘1’b for all widgets that report EPSS set to one
‘1’b and that have host programmable settings and resets all settings.
Single Function Group Reset, Link Reset or BITCLK stopped will not cause the PS-SettingsReset bit to be
set to ‘1’b. All settings will persist across these events.
The PS-SettingsReset will be reported at the individual widget level and at the Audio Function Group level.
The PS-SettingsReset bit for the Audio Function Group is handled differently than at the widget level. For
the Audio Function Group the PS-SettingsReset bit is set to ‘1’b when any widget sets its PS-SettingsReset
to ‘1’b. The Audio Function Group’s PS-SettingsReset bit is the logical “or” of all the PS-SettingsReset bits,
but is latched so that it can be reset independently and not require all the individual widget PS-SettingsReset
bits be reset. This allows a simple poll by the host software to detect when some settings have been re-
set/changed. For widgets that do not support the EPSS bit, reporting PS-SettingsReset is not required.
If the PS-SettingsReset bit is set to ‘1’b, then this bit for individual widgets will be cleared to ‘0’b on receipt
of any “Set” verb to that widget; or after responding to a “Get” Power State verb to that widget.
Bit settings within converters and pin widgets that software changed from their defaults will not be changed
by hardware across any Dx state transition, single function group resets or link resets. Table 1 on page 29
outlines how the handling of setting persistence should be performed across Dx states, clock stopping and
resets. Because the CS4207 supports EPSS, the use of PS-SettingsReset to report that settings have been
reset (changed) is required.
D
CLR
Q
CLK
‘1’b
Power On Reset or
Double Function
Group Reset
Get “Power State”
Verb
Function Group
PS_Settings Reset Bit
Figure 8. PS-Settings Reset Behavior
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