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參數(shù)資料
| 型號： | CS61584A-IQ3Z |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 14/47頁 |
| 文件大小： | 0K |
| 描述： | IC LINE INTERFACE T1/E1 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.3V，5V |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1713 |
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CS61584A
DS261PP5
21
DS261PP5
8.3
Bipolar Violation Detection
During Host mode operation, a bipolar violation
(BPV) is detected by the receiver and reported us-
ing the Latched-BPV bit in the Status registers. If
CODER = 1 in the Control A registers, the RNEG
pin becomes the BPV output strobe pin that is set
high for one bit period on detection of a BPV. Note
that B8ZS (or HDB3) zero substitutions are not
flagged as bipolar violations if the B8ZS (or
HDB3) decoder has been enabled (CODER = 1 and
AMI-R = 0 in the Control A registers).
8.4
Excessive Zeros Detection
During Host mode operation if CODER = 1 and
EXZ = 1 in the Control A register, the BPV output
pin is OR’ed with receive excessive zero events. In
AMI mode when AMI-Rx = 1, the BPV pin is set
high for one bit period when 16 or more consecu-
tive zeros are received. In B8ZS mode when AMI-
Rx = 0, the BPV pin is set high for one bit period
when 8 or more consecutive zeros are received.
This is in accordance with the ANSI T1.231 speci-
fication. For E1 operation with HDB3 disabled, the
excessive zeros detection is also disabled. For E1
with HDB3 enabled the BPV pin goes high for ev-
ery set of 4 consecutively received zeros.
8.5
Loss of Signal
During Hardware mode and Host mode operation,
the loss of signal (LOS) condition is detected by the
receiver and reported when the LOS pin is set high.
Loss of signal is indicated when 175 ±15 consecu-
tive zeros are received, or when the receive
(RTIP/RRING) signal level drops below the receiv-
er sensitivity of the device. The LOS condition is
exited according to the ANSI T1.231-1993 criteria
that requires a minimum 12.5% ones density signal
over 175 ±75 bit periods with no more than 100
consecutive zeros. During LOS, recovered data is
squelched and zeroes are output on RPOS/RNEG
(RDATA).
During Host mode operation, LOS is reported us-
ing the LOS and Latched-LOS bits in the Status
registers. Note that both the LOS pin and register
indications are available in Host mode operation.
The LOS pin and/or bit is set high when the device
is reset, in power-up, or a channel is powered-down
and returns low when data is recovered by the re-
ceiver.
During LOS condition the RPOS (RDATA),
RNEG pins are forced low, except when LLOOP1
(digital loopback) is enabled, or when the AAO
(Automatic All Ones) bit is set in the channel 1
mask register. Setting the AAO bit high forces un-
framed all ones pattern out on the RPOS (RDA-
TA), RNEG pins when LOS condition occurs.
When the jitter attenuator is in the receive path and
LOS occurs, the frequency of the last valid recov-
ered signal is held at RCLK. When the jitter atten-
uator is not in the receive path, the output
frequency becomes the frequency of the reference
clock.
8.6
Transmit All Ones
During Hardware mode operation, transmit all ones
(TAOS) is selected by setting the TAOS pin high.
During Host mode, TAOS is controlled using the
TAOS bit in the Control B registers.
Selecting TAOS causes continuous ones to be
transmitted to the line on TTIP and TRING at the
frequency of REFCLK. In this mode, the transmit
data inputs TPOS and TNEG (or TDATA) are ig-
nored. A TAOS request overrides the data transmit-
ted to the line interface during local and remote
loopbacks. Note that the CLKLOST interrupt is
not available for TCLK in the TAOS mode.
8.7
Receive All Ones
During Host mode operation, the data at RPOS and
RNEG (or RDATA) may be forced to output an un-
framed all-ones pattern by setting both the
LLOOP1 and LLOOP2 bits in the Control B regis-
ter to "1". An automatic Receive All Ones (AAO)
CS61584A
DS261F1
21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS61584A-IQ3ZR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5Z | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5ZR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584-IL3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface |
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