參數(shù)資料
型號(hào)： CS61584A-IQ3Z
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 17/47頁(yè)
文件大?。?/td> 0K
描述： IC LINE INTERFACE T1/E1 64LQFP
標(biāo)準(zhǔn)包裝： 160
接口： 并行/串行
電源電壓： 3.3V，5V
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤(pán)
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
其它名稱： 598-1713
CS61584A
24
DS261PP5
Latched-LOS: Set high on the rising edge of the
loss of signal condition. Reading the Status register
clears the Latched-LOS bit and deactivates the INT
pin. Refer to the timing diagram in Figure 18.
AIS: Set high while the alarm indication signal is
detected. Reading the Status register does not clear
the AIS bit. An AIS interrupt is generated only on
the falling edge of the AIS alarm condition. The
Latched-AIS bit generates an interrupt on the rising
edge of AIS. Refer to the timing diagram in
Figure 18.
Status Register (Channel 1)
Serial Port Address: 0x10; Parallel Port Address: 0xY0
Bit
Description
Definition
Reset
Value
10
7
LOS1
LOS currently detected
no LOS
1
6
Latched-LOS1
LOS event since last read
no LOS
1
5
AIS1
AIS currently detected
no AIS
0
4
Latched-AIS1
AIS event since last read
no AIS
0
3
Latched-BPV1
BPV event since last read
no BPV
0
2
Latched-Overflow1
Pulse overflow since last read
no overflow
0
1
Latched-Reset
Reset event since last read
no reset
1
0
Interrupt1
Interrupt event since last read
no interrupt
1
Status Register (Channel 2)
Serial Port Address: 0x11; Parallel Port Address: 0xY1
Bit
Description
Definition
Reset
Value
10
7
LOS2
LOS currently detected
no LOS
1
6
Latched-LOS2
LOS event since last read
no LOS
1
5
AIS2
AIS currently detected
no AIS
0
4
Latched-AIS2
AIS event since last read
no AIS
0
3
Latched-BPV2
BPV event since last read
no BPV
0
2
Latched-Overflow2
Pulse overflow since last read
no overflow
0
1
Latched-CLKLOST
TCLK or REFCLK absent
TCLK and REFCLK present
0
Interrupt2
Interrupt event since last read
no interrupt
1
Table 5. Status Registers
AIS/LOS Currently Active
(AIS/LOS bit & AIS/LOS pin)
Latched LOS
(Latch AIS/LOS bit)
Read AIS/LOS bits
"Short" AIS/LOS event
"Long" AIS/LOS event
Set by start
of AIS/LOS
Cleared by read
Set by Change
of AIS/LOS
Cleared by read
Interrupt
(INT)
Figure 18. Alarm Indication Event Relationships
CS61584A
24
DS261F1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS61584A-IQ3ZR 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5Z 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5ZR 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584-IL3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface
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