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參數(shù)資料
| 型號(hào)： | CS61584A-IQ3Z |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 8/47頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE INTERFACE T1/E1 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.3V，5V |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁(yè)面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1713 |
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CS61584A
16
DS261PP5
The line receiver contains all the necessary clock
and data recovery circuits.
The jitter attenuator meets AT&T 62411 require-
ments when using either a 1X or 8X reference
clock supplied by either a quartz crystal, crystal os-
cillator, or external reference at the REFCLK input
pin.
2.1
AT&T 62411 Customer Premises
Application
The AT&T 62411 specification applies to the T1
interface between the customer premises and the
carrier, and must be implemented by the customer
premises equipment in order to connect to the
AT&T network.
In 62411 applications, the management of jitter is a
very important design consideration. Typically, the
jitter attenuator is placed in the receive path of the
CS61584A to reduce the jitter input to the system
synchronizer. The jitter attenuated recovered clock
is used as the input to the transmit clock to imple-
ment a loop-timed system. A Stratum 4 (±32 ppm)
quality clock or better should be input to REFCLK.
Note that any jitter present on the reference clock
will not be filtered by the jitter attenuator.
2.2
Asynchronous Multiplexer
Application
Asynchronous multiplexers accept multiple T1/E1
lines (which are asynchronous to each other), and
combine them into a higher speed transmission rate
(e.g. M13 muxes and SONET muxes). In these sys-
tems, the jitter attenuator is placed in the transmit
path of the CS61584A to remove the gapped clock
jitter input by the multiplexer to TCLK. Because
the transmit clock is jittered, the reference clock to
the CS61584A is provided by an external source
operating at 1X or 8X the data rate. Because T1/E1
framers are not usually required in asynchronous
multiplexers, the B8ZS/AMI/HDB3 coders in the
CS61584A are activated to provide data interfaces
on TDATA and RDATA.
2.3
Synchronous Application
A typical example of a synchronous application is
a T1 card in a central office switch or a 0/1 digital
cross-connect system. These systems place the jit-
ter attenuator in the receive path to reduce the jitter
presented to the system. A Stratum 3 or better sys-
tem clock is input to the CS61584A transmit and
reference clocks.
3. TRANSMITTER
The transmitter accepts data from a T1 or E1 sys-
tem and outputs pulses of appropriate shape to the
line. The transmit clock (TCLK) and transmit data
(TPOS and TNEG, or TDATA) are supplied syn-
chronously. Data is sampled on the falling edge of
the TCLK input.
During Hardware mode operation, the configura-
tion pins (CON[3:0]) control transmitted pulse
shapes, transmitter source impedance, receiver
slicing level, and driver tristate as shown in
Table 1. During Host mode operation, the configu-
ration is established by the CON[3:0] bits in the
Control B registers. Typical output pulses are
fully pre-defined by circuitry in the CS61584A,
and are fully compliant with appropriate standards
when used with our application guidelines in stan-
dard installations. Both channels must be operated
at the same line rate (both T1 or both E1).
Host mode operation permits arbitrary transmit
pulse shapes to be created and downloaded to the
CS61584A. These custom pulse shapes can be used
to compensate for waveform degradation caused by
non-standard cables, transformers, or protection
circuitry (refer to the Arbitrary Waveform Regis-
ters section).
Note that the pulse width for Part 68 Option A
(324 ns) is narrower than the optimal pulse width
for DSX-1 (350 ns). The CS61584A automatically
adjusts the pulse width based on the configuration
selection.
CS61584A
16
DS261F1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS61584A-IQ3ZR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5Z | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5ZR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584-IL3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface |
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