參數(shù)資料
型號： CXK77B3640AGB
廠商： Sony Corporation
英文描述： 4Mb Late Write HSTL High Speed Synchronous SRAM(128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位))
中文描述： 4Mb的后寫入HSTL高速同步SRAM（128K的x 36Bit）（4分位，寫延遲，高速邏輯收發(fā)（HSTL），高速同步靜態(tài)隨機(jī)存儲器（128K的× 36位））
文件頁數(shù)： 26/33頁
文件大?。?/td> 284K
代理商： CXK77B3640AGB
4Mb, Sync LW, HSTL, rev 1.5
26 / 33
July 23, 1998
SONY
CXK77B3640AGB / CXK77B1840AGB
Preliminary
Test Mode Description
Functional Description
These devices provide a JTAG boundary scan interface using a limited set of IEEE std. 1149.1 functions.
The test mode is intended to provide a mechanism for testing the interconnect between master (proces-
sor, controller, etc.), SRAMs, other components and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP controller, Instruction
register, Boundary Scan register and Bypass register.
JTAG Inputs/Outputs are LVTTL compatible only.
Test Access Port (TAP)
4 pins as defined in the Pin Description table are used to perform JTAG functions. The TDI input pin is
used to scan test data serially into one of three registers (Instruction register, Boundary Scan register and
Bypass register). TDO is the output pin used to scan test data serially out. The TDI pin sends the data
into LSB of the selected register and the MSB of the selected register feeds the data to TDO. The TMS
input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs
on TDI and TMS are registered on the rising edge of TCK clock. The output data on TDO is presented
on the falling edge of TCK. TDO driver is in active state only when TAP controller is in Shift-IR state
or in Shift-DR state.
TCK, TMS, TDI must be tied low when JTAG is not used.
TAP Controller
16 state controller is implemented as specified in IEEE std. 1149.1.
The controller enters reset state in one of two ways:
1. Power up.
2. Apply a logic 1 on TMS input pin on 5 consecutive TCK rising edges.
Instruction Register (3 bits)
The JTAG Instruction register consists of a shift register stage and parallel output latch. The register is
3 bits wide and is encoded as follow:
Octal
MSB..........LSB
Instruction
0
0
0
0
Bypass
1
0
0
1
IDCODE. Read device ID
2
0
1
0
Sample-Z. Sample Inputs and tri-state DQs
3
0
1
1
Bypass
4
1
0
0
Sample. Sample Inputs.
5
1
0
1
Private. Manufacturer use only.
6
1
1
0
Bypass
7
1
1
1
Bypass
相關(guān)PDF資料
PDF描述
CXK77B1840AGB 4Mb Late Write HSTL High Speed Synchronous SRAM(256K x 18Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (256K x 18位))
CXK77B3641GB 4Mb Late Write LVTTL High Speed Synchronous SRAM (128K x 36Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (128K x 36位))
CXK77V3211Q-12 Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Color:White/Red; Cable/Wire MIL SPEC:MIL-W-16878/1 Type B; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
CXK77V3211Q-14 Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Color:White/Red; Cable/Wire MIL SPEC:MIL-W-16878/1 Type B; Conductor Material:Copper; Conductor Plating:Tin; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
CXK77V3211Q 32768-word by 32-bit High Speed Synchronous Static RAM(32768字 × 32位高速同步靜態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXK77B3640GB-45 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
CXK77B3640GB-4A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
CXK77B3641GB-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
CXK77B3641GB-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
CXK77K18R320GB 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
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