參數(shù)資料
型號(hào)： CY39200V208-181NTXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 8.5 ns, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208
文件頁(yè)數(shù)： 15/86頁(yè)
文件大?。?/td> 2802K
代理商： CY39200V208-181NTXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 22 of 86
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).[15] Apply following adjustments if the inputs and outputs
are configured to operate at other standards.
tINDUTY
40
60
40
60
40
60
40
60
40
60
%
fPLLO[14]
6.2
266
6.2
266
6.2
266
6.2
200
6.2
200
MHz
fPLLI[14]
12.5
133
12.5
133
12.5
133
12.5
100
12.5
100
MHz
fPLLVCO
100
266
100
266
100
266
100
266
100
266
MHz
PSAPLLI
–0.3
+0.3
–0.3
+0.3
–0.3
+0.3
–0.3
+0.3
–0.3
+0.3
%
fMPLLI
50
KHz
JTAG Parameters
tJCKH
25
ns
tJCKL
25
ns
tJCP
50
ns
tJSU
10
ns
tJH
10
ns
tJCO
20
ns
tJXZ
20
ns
tJZX
20
ns
Switching Characteristics—Parameter Values Over the Operating Range (continued)
Parameter
233
200
181
125
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
I/O Standard
Output Delay Adjustments
Input Delay Adjustments
Fast Slew Rate
Slow Slew Rate
(additional delay to fast slew rate)
tIOD
tEA
tER
tIODSLOW
tEASLOW
tERSLOW
tIOIN
tCKIN
tIOREGPIN
LVTTL – 2 mA
2.75
0
2.6
2.0
0
LVTTL – 4 mA
1.8
0
2.5
2.0
0
LVTTL – 6 mA
1.8
0
2.5
2.0
0
LVTTL – 8 mA
1.2
0
2.4
2.0
0
LVTTL – 12 mA
0.6
0
2.3
2.0
0
LVTTL – 16 mA
0.16
0
2.0
0
LVTTL – 24 mA
0
1.6
2.0
0
LVCMOS
0
2.0
0
LVCMOS3
0.14
0.05
0
2.0
0.1
0.2
LVCMOS2
0.41
0.1
0
2.0
0.2
0.4
LVCMOS18
1.6
0.7
0.1
2.1
2.0
0.5
0.4
0.3
3.3V PCI
–0.14
0
2.0
0
GTL+
0.02[16]
0.6[16]
0.9[16]
2.0
0.5
0.4
0.2
SSTL3 I
–0.15
0.3
0.1
2.0
0.5
0.3
SSTL3 II
–0.4
0.2
0
2.0
0.5
0.3
Notes:
14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200V208-200BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-200BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-200BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-200BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V208-200MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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