參數(shù)資料
型號(hào)： CY8C22213-24SIT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO20
封裝： 0.300 INCH, MO-119, SOIC-20
文件頁(yè)數(shù)： 59/304頁(yè)
文件大?。?/td> 2956K
代理商： CY8C22213-24SIT
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December 22, 2003
Document No. 38-12009 Rev. *D
59
CY8C22xxx Preliminary Data Sheet
6. General Purpose IO (GPIO)
together as DM[2:0]. Drive modes are shown in
Table 6-3
.
For analog IO, the drive mode should be set to one of the
Hi-Z modes, either 010b or 110b. The 110b mode has the
advantage that the block’s digital input buffer is disabled, so
no “crowbar” current flows even when the analog input is not
close to either power rail. When digital inputs are needed on
the same pin as analog inputs, the 010b Drive mode should
be used. If the 110b Drive mode is used, the pin will always
be read as a zero by the CPU and the pin will not be able to
generate a useful interrupt. (It is not strictly required that a
Hi-Z mode be selected for analog operation).
For global input modes, the drive mode must be set to 010b.
This GPIO provides a default drive mode of high impedance
(Hi-Z). This is achieved by forcing the reset state of all
PRTxDM1 and PRTxDM2 registers to FFh.
The resistive drive modes place a resistance in series with
the output, for low outputs (mode 000b) or high outputs
(mode 011b). Strong drive mode 001b gives the fastest
edges at high DC drive strength. Mode 101b gives the same
drive strength but with slower edges. The Open drain modes
(100b and 111b) also use the slower edge rate drive. These
modes enable open drain functions such as I
2
C mode 111b
(although the slow edge rate is not slow enough to meet the
I
2
C fast mode specification).
For additional information, reference the
PRTxDM2 register
on page 89
, the
PRTxDM0 register on page 145
, and the
PRTxDM1 register on page 146
.
6.2.5
PRTxICx Registers
The interrupt mode for the pin is determined by bits in two
registers: PRTxIC1 and PRTxIC0. These are referred to as
IM1 and IM0, or together as IM[1:0].
There are four possible interrupt modes for each port pin.
Two mode bits are required to select one of these modes
and these two bits are spread into two different registers
(PRTxIC0 and PRTxIC1). The bit position of the effected
port pin (Example: Pin[2] in Port 0) is the same as the bit
position of each of the Interrupt Control register bits that
control the interrupt mode for that pin (Example: Bit[2] in
PRT0IC0 and bit[2] in PRT0IC1). The two bits from the two
registers are treated as a group.
The interrupt mode must be set to one of the non-zero
modes listed in
Table 6-4
, in order to get an interrupt from
the pin.
The GPIO interrupt mode “disabled” (00b) disables inter-
rupts from the pin, even if the GPIO’s bit interrupt enable is
on (from the PRTxIE register).
Interrupt mode 01b means that the block will assert the
interrupt line (INTO) when the pin voltage is low, providing
the block’s bit interrupt enable line is set (high).
Interrupt mode 10b means that the block will assert the
interrupt line (INTO), when the pin voltage is high, providing
the block’s bit interrupt enable line is set (high).
Interrupt mode 11b means that the block will assert the inter-
rupt line (INTO) when the pin voltage is the opposite of the
last state read from the pin (again providing the block’s bit
interrupt enable line is set high). This mode switches
between low mode and high mode, depending on the last
value that was read from the port during reads of the data
register (PRTxDR). If the last value read from the GPIO was
0, the GPIO will subsequently be in interrupt high mode. If
the last value read from the GPIO was 1, the GPIO will then
be in interrupt low mode.
Figure 6-3. GPIO Interrupt Mode 11b
Figure 6-3
assumes that the GIE is set, GPIO interrupt mask
is set, and that the GPIO interrupt mode has been set to
11b. The change interrupt mode is different from the other
modes, in that it relies on the value of the GPIO’s read latch
to determine if the pin state has changed. Therefore, the
port that contains the GPIO in question must be read during
Table 6-3. Pin Drive Modes
Drive Mode
DM[2:0]
000b
001b
010b
Pin State
Description
Resistive pull down
Strong drive
High impedance
Strong high, resistive low
Strong high, strong low
Hi-Z high and low, digital input
enabled
Resistive high, strong low
Slow strong high, Hi-Z low
Slow strong high, slow strong low
Hi-Z high and low, digital input dis-
abled (for zero power) (
reset state
)
Slow strong low, Hi-Z high
011b
100b
101b
110b
Resistive pull up
Open drain high
Slow strong drive
High impedance,
analog (
reset state
)
Open drain low
111b
Table 6-4. GPIO Interrupt Modes
Interrupt Mode IM[1:0]
00b
01b
10b
11b
Description
Bit interrupt disabled, INTO de-asserted
Assert INTO when PIN = low
Assert INTO when PIN = high
Assert INTO when PIN = change from last
read
Last Value Read From Pin was 0
Pin State Waveform
(a)
GPIO pin
interrupt
enable set
Interrupt
occurs
Pin State Waveform
(b)
GPIO pin
interrupt
enable set
Interrupt
occurs
Last Value Read From Pin was 1
Pin State Waveform
(c)
GPIO pin
interrupt
enable set
Interrupt
occurs
Pin State Waveform
(d)
GPIO pin
interrupt
enable set
Interrupt
occurs
相關(guān)PDF資料
PDF描述
CY8C24794-SPAX PSoCTM Mixed-Signal Array
CY8C24794-SPE PSoCTM Mixed-Signal Array
CY8C24794-SPI Explosion-Proof Limit Switches Series CX: Short Housing: Top Plunger; 1NC 1NO SPDT Snap Action; Number of internal basic switches BZ: 1; 0.75 in - 14NPT conduit
CY8C24794-SPLFX Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-1
CY8C24794-SPPVX Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY8C22345 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip
CY8C22345-12PVXE 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
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CY8C22345-24PVXAT 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
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