參數(shù)資料
型號： DAC757IDGSR
廠商： Texas Instruments, Inc.
英文描述： QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉換器
文件頁數(shù)： 11/31頁
文件大小： 783K
代理商： DAC757IDGSR
www.ti.com
_
+
Resistor String
Ref-
Ref+
DAC Register
V
OUT
50 k
50 k
V
DD
GND
70 k
V
OUT
V
DD
D
4096
(1)
V
DD
To Output
Amplifier
R
R
R
R
GND
DAC7574
SLAS375–JUNE 2003
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC7574 consists of a string DAC followed by an output buffer amplifier. Figure 29
shows a generalized block diagram of the DAC architecture.
Figure 29. R-String DAC Architecture
The input coding to the DAC7574 is unsigned binary, which gives the ideal output voltage as:
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 30. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
Figure 30. Typical Resistor String
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to V
DD
. It is capable of driving a load of 2 k
in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/μs
with a half-scale settling time of 8 μs with the output unloaded.
I
2
C Interface
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is
idle
, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus through
open drain I/O pins, SDA and SCL. A
master
device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A
slave
device receives and/or
transmits data on the bus under control of the master device.
11
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