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參數(shù)資料
| 型號： | DAC757IDGSR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 783K |
| 代理商： | DAC757IDGSR |
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SLAVE ADDRESS R/W
A Ctrl-Byte
A MS-Byte A
LS-Byte
A/A
P
”0” (write)
Data Transferred
(n* Words + Acknowledge)
Word = 12 Bit
From Master to DAC7574
From DAC7574 to Master
A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
DAC7574 I
2
C-SLAVE ADDRESS:
1
0
0
1
1
A1
A0
R/W
MSB
LSB
Factory Preset
A0 = I
2
C Address Pin
A1 = I
2
C Address Pin
S
‘0’ = Write to DAC7574
‘1’ = Read from DAC7574
DAC7574
SLAS375–JUNE 2003
LDAC Functionality
Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal
that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the
channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four
DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only
be used after the buffers temporary registers are properly updated through software.
DAC7574 Registers
Table 3. DAC7574 Architecture Register Descriptions
Register
Description
CTRL[7:0]
Stores 8-bit wide control byte sent by the master
Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit
power-down data.
MSB[7:0]
LSB[7:0]
Stores the 4 least significant bits of unsigned binary data sent by the master.
TRA[13:0], TRB[13:0],
TRC[13:0], TRD[13:0]
14-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 12
LSBs store data.
DRA[13:0], DRB[13:0],
DRC[13:0], DRD[13:0]
14-bit DAC registers for each channel. Two MSBs store power-down information, 12 LSBs store DAC data.
An update of this register means a DAC update with data or power-down.
DAC7574 as a Slave Receiver - Standard and Fast Mode
Figure 35 shows the standard and fast mode master transmitter addressing a DAC7574
Slave Receiver
with a
7-bit address.
Figure 35. Standard and Fast Mode: Slave Receiver
17
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