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參數(shù)資料
| 型號： | DAC757IDGSR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 20/31頁 |
| 文件大?。?/td> | 783K |
| 代理商： | DAC757IDGSR |
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DAC7574
SLAS375–JUNE 2003
Master Transmitter Writing to a Slave Receiver (DAC7574) in HS Mode
When writing data to the DAC7574 in HS-mode, the master begins to transmit what is called the
HS-Master
Code
(0000 1XXX) in F/S-mode. No device is allowed to acknowledge the
HS-Master Code
, so the
HS-Master
Code
is followed by a NOT acknowledge.
The master then
switches
to HS-mode and issues a
repeated start
condition, followed by the address byte (with
R/W = 0) after which the DAC7574 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC7574. The LSB of the control byte (PD0-Bit) determines
if the following data is
power-down data
or regular data.
With (PD0-Bit = 0) the DAC7574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –
HIGH-BYTE – LOW-BYTE...., until a STOP condition or
repeated start
condition on the I
2
C-Bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC7574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC7574) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS mas-
ter code
NONE
Not Acknowledge
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (
R/W=0
)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
0
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0=0
)
DAC7574
DAC7574 Acknowledges
Master
D11
D10
D9
D8
D7
D6
D5
D4
Writing data word, MSB
DAC7574
DAC7574 Acknowledges
Master
D3
D2
D1
D0
x
x
x
x
Writing data word, LSB
DAC7574
DAC7574 Acknowledges
Data or Stop or Repeated Start(1)
Master
Data or done(2)
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS mas-
ter code
NONE
Not Acknowledge
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (
R/W = 0
)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 2
0
Buff Sel 1
Buff Sel 0
PD0
Control Byte (
PD0=1
)
DAC7574
DAC7574 Acknowledges
Master
PD1
PD2
0
0
0
0
0
0
Writing data word, high byte
DAC7574
DAC7574 Acknowledges
Master
0
0
0
0
x
x
x
x
Writing data word, low byte
DAC7574
DAC7574 Acknowledges
Stop or repeated start(1)
Master
Done
(1)
(2)
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
Once DAC7574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
20
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