參數(shù)資料
型號(hào)： DAC757IDGSR
廠商： Texas Instruments, Inc.
英文描述： QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 25/31頁(yè)
文件大?。?/td> 783K
代理商： DAC757IDGSR
www.ti.com
DAC7574
SLAS375–JUNE 2003
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC7574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC7574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
k
can be driven by the DAC7574 while achieving a typical load regulation of 1%. As the load resistance drops
below 2 k
, the load regulation error increases. When the outputs of the DAC are driven to the positive rail under
resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this
occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within
approximately the top 20 mV of the DAC’s digital input-to-voltage output transfer characteristic. The reference
voltage applied to the DAC7574 may be reduced below the supply voltage applied to V
DD
in order to eliminate
this condition if good linearity is a requirement at full scale (under resistive loading conditions).
CROSSTALK
The DAC7574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.5 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at
one channel, and measured at the remaining output channel) is typically under -100 dB.
OUTPUT VOLTAGE STABILITY
The DAC7574 exhibits excellent temperature stability of
±
3 ppm/
°
C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a
±
25 μV window
for a
±
1
°
C ambient temperature change. Combined with good dc noise performance and true 12-bit differential
linearity, the DAC7574 becomes a perfect choice for closed-loop control applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 12-bit accurate range of the DAC7574 is achievable within 10 μs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 μs. The
high-speed serial interface of the DAC7574 is designed in order to support up to 188ksps update rate. For
full-scale output swings, the output stage of each DAC7574 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 μV) given that the code-to-code transition does not cross an Nx256 code boundary. Due to internal
segmentation of the DAC7574, code-to-code glitches occur at each crossing of an Nx256 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 μs. Sufficient bypass capacitance is required
to ensure 10 μs settling under capacitive loading. To observe the settling performance under resistive load
conditions, the power supply (hence DAC7574 reference supply) must settle quicker than the DAC7574.
25
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