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參數資料
| 型號： | DC575A |
| 廠商： | Linear Technology |
| 文件頁數： | 14/48頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2410 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC575A Design File DC575A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數量： | 2 |
| 位數： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2410 |
| 已供物品： | 板 |
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LTC2410
21
APPLICATIO S I FOR ATIO
WU
U
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as tEOCtest), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after VCC exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Figure 10. Internal Serial Clock, Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB24
MSB
SIG
BIT 5
BIT 0
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2410 F10
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
214
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
2-WIRE
INTERFACE
1
F
2.7V TO 5.5V
LTC2410
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