參數(shù)資料
型號： DC575A
廠商： Linear Technology
文件頁數(shù)： 29/48頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2410
軟件下載： QuikEval System
設計資源： DC575A Design File
DC575A Schematic
標準包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 2
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2410
已供物品： 板
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LTC2410
35
APPLICATIO S I FOR ATIO
WU
U
Simultaneous Sampling with Two LTC2410s
One such application is synchronizing multiple LTC2410s,
see Figure 45. The start of conversion is synchronized to
the rising edge of CS. In order to synchronize multiple
LTC2410s, CS is a common input to all the ADCs.
To prevent the converters from autostarting a new con-
version at the end of data output read, 31 or fewer SCK
clock signals are applied to the LTC2410 instead of 32 (the
32nd falling edge would start a conversion). The exact
timing and frequency for the SCK signal is not critical
since it is only shifting out the data. In this case, two
LTC2410’s simultaneously start and end their conversion
cycles under the external control of CS.
Increasing the Output Rate Using Mulitple LTC2410s
A second application uses multiple LTC2410s to increase
the effective output rate by 4
×, see Figure 46. In this case,
four LTC2410s are interleaved under the control of sepa-
rate CS signals. This increases the effective output rate
from 7.5Hz to 30Hz (up to a maximum of 60Hz). Addition-
ally, the one-shot output spectrum is unfolded allowing
further digital signal processing of the conversion results.
SCK and SDO may be common to all four LTC2410s. The
four CS rising edges equally divide one LTC2410 conver-
sion cycle (7.5Hz for 60Hz notch frequency). In order to
synchronize the start of conversion to CS, 31 or less SCK
clock pulses must be applied to each ADC.
Both the synchronous and 4
× output rate applications use
the external serial clock and single cycle operation with
reduced data output length (see Serial Interface Timing
Modes section and Figure 6). An external oscillator clock
is applied commonly to the FO pin of each LTC2410 in
order to synchronize the sampling times. Both circuits
may be extended to include more LTC2410s.
Figure 45. Synchronous Conversion—Extendable
31 OR LESS CLOCK CYCLES
CS
SCK1
SCK2
2410 F45
SDO1
SDO2
31 OR LESS CLOCK CYCLES
LTC2410
#1
VCC
REF+
REF –
IN+
IN –
GND
FO
SCK
SDO
CS
SCK2
SCK1
CS
SDO1
SDO2
LTC2410
#2
VCC
REF+
REF –
IN+
IN –
GND
FO
SCK
SDO
CS
CONTROLLER
EXTERNAL OSCILLATOR
(153,600HZ)
VREF+
VREF–
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