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參數(shù)資料
| 型號： | DC575A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2410 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC575A Design File DC575A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2410 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | DC590B-ND - BOARD DEMO USB SERIAL CONTROLLER LTC2410IGN#PBF-ND - IC ADC 24BIT DIFF INP/REF 16SSOP LTC2410CGN#TRPBF-ND - IC ADC 24BIT DIFF INP/REF 16SSOP LTC2410IGN#TRPBF-ND - IC ADC 24BIT DIFF INP/REF 16SSOP LTC2410CGN#PBF-ND - IC ADC 24BIT DIFF INP/REF 16SSOP LTC2410CGN#TR-ND - IC ADC 24BIT DIFF INP/REF 16SSOP LTC2410IGN#TR-ND - IC ADC 24BIT DIFF INP/REF 16SSOP LTC2410IGN-ND - IC A/D CONV 24BIT MICRPWR 16SSOP LTC2410CGN-ND - IC ADC 24BIT DIFF INP/REF 16SSOP |
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LTC2410
11
TEST CIRCUITS
APPLICATIO S I FOR ATIO
WU
U
FU CTIO AL BLOCK DIAGRA
UU
W
Figure 2. LTC2410 State Transition Diagram
CONVERTER OPERATION
Converter Operation Cycle
The LTC2410 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface
(see Figure 1). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2410 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫
GND
VCC
IN+
IN–
SDO
SCK
REF+
REF –
CS
FO
(INT/EXT)
2410 FD
–+
+
–
1.69k
SDO
2410 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
1.69k
SDO
2410 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
CONVERT
SLEEP
DATA OUTPUT
2410 F02
TRUE
FALSE
CS = LOW
AND
SCK
Figure 1. Functional Block Diagram
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
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