SCL (Pin 6): Serial Clock Pin of the I2
參數(shù)資料
型號(hào)： DC951A
廠商： Linear Technology
文件頁(yè)數(shù)： 3/40頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2481
軟件下載： QuikEval System
設(shè)計(jì)資源： DC951A Design File
DC951A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： I²C，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2481
已供物品： 板
相關(guān)產(chǎn)品： LTC2481HDD#TRPBF-ND - IC ADC DELTA SIGMA 16BIT 10DFN
LTC2481HDD#PBF-ND - IC ADC 16BIT I2C 7.5SPS 10DFN
LTC2481CDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN
LTC2481IDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN
LTC2481IDD#PBF-ND - IC ADC 16BIT I2C 10-DFN
LTC2481CDD#PBF-ND - IC ADC 16BIT I2C 10-DFN
LTC2481
11
2481fc
PIN FUNCTIONS
FUNCTIONAL BLOCK DIAGRAM
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2481 can only act as a slave and the SCL pin only ac-
cepts external serial clock. Data is shifted into the SDA pin
on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
SDA (Pin 7): Bidirectional Serial Data Line of the I2C Inter-
face. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device conguration bits are input through the
SDA pin. At data input mode, the pin is high impedance;
while at data output mode, it is an open-drain N-channel
driver and therefore an external pull-up resistor or current
source to VCC is needed.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
congured as a three state (LOW, HIGH, or Floating) ad-
dress control bit for the device I2C address.
CA0/f0 (Pin 10): Chip Address Control Pin/External Clock
Input Pin. When no transition is detected on the CA0/f0
pin, it is a two state (HIGH or Floating) address control
bit for the device I2C address. When the pin is driven by
an external clock signal with a frequency fEOSC of at least
10kHz, the converter uses this signal as its system clock
and the fundamental digital lter rejection null is located
at a frequency fEOSC/5120 and sets the Chip Address CA0
internally to a HIGH.
6
7
4
5
9
10
3RD ORDER
ADC
REF+
IN+
1
REF+
IN–
REF–
(1-256)
GAIN
I2C
SERIAL
INTERFACE
TEMP
SENSOR
MUX
SCL
2
VCC
3
REF–
8
GND
CA0/f0
2481 FD
SDA
CA1
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
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