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參數(shù)資料
| 型號： | DC951A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2481 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC951A Design File DC951A Schematic |
| 標準包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2481 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | LTC2481HDD#TRPBF-ND - IC ADC DELTA SIGMA 16BIT 10DFN LTC2481HDD#PBF-ND - IC ADC 16BIT I2C 7.5SPS 10DFN LTC2481CDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481IDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481IDD#PBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481CDD#PBF-ND - IC ADC 16BIT I2C 10-DFN |
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LTC2481
17
2481fc
APPLICATIONS INFORMATION
Initiating a New Conversion
When the LTC2481 nishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device
is ready for Read/Write operations. After the device ac-
knowledges a Read or Write request, the device exits the
sleep state and enters the data input/output state. The data
input/output state concludes and the LTC2481 starts a new
conversion once a STOP condition is issued by the master
or all 24 bits of data are read out of the device.
During the data read cycle, a stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the 9th clock cycle of a byte read when the
bus is free (the ACK/NACK cycle).
LTC2481 Address
The LTC2481 has two address pins, enabling one in 6
possible addresses, as shown in Table 5.
Table 5. LTC2481 Address Assignment
CA1
CA0/f0 *
Address
LOW
HIGH
001 01 00
LOW
Floating
001 01 01
Floating
HIGH
001 01 11
Floating
010 01 00
HIGH
010 01 10
HIGH
Floating
010 01 11
* CA0/f0 is treated as HIGH when driven by a valid external clock.
InadditiontothecongurableaddresseslistedinTable5,the
LTC2481 also contains a global address (1110111) which
may be used for synchronizing multiple LTC2481s.
OPERATION SEQUENCE
The LTC2481 acts as a transmitter or receiver. The device
may be programmed to perform several functions. These
include measuring an external differential input signal or
an integrated temperature sensor, setting a programmable
gain (from 1 to 256), selecting line frequency rejection
(50Hz, 60Hz, or simultaneous 50Hz and 60Hz), and a 2x
speed up mode.
Continuous Read
In applications where the conguration does not need to
change for each conversion cycle, the conversion result
can be continuously read. The conguration remains
unchanged from the last value written into the device.
If the device has not been written to since power up, the
conguration is set to the default value (Input External,
GAIN=1, simultaneous 50Hz/60Hz rejection, and 1x
speed mode). The operation sequence is shown in Figure
6. When the conversion is nished, the device may be
addressed for a read operation. At the end of a read
operation, a new conversion begins. At the conclusion
of the conversion cycle, the next result may be read
using the method described above. If the conversion
cycle is not concluded and a valid address selects the
device, the LTC2481 generates a NACK signal indicating
the conversion cycle is in progress.
Figure 4. Timing Diagram for Reading from the LTC2481
SLEEP
DATA OUTPUT
START BY
MASTER
ACK BY
LTC2481
ACK BY
MASTER
NAK BY
MASTER
PG2
PG1
PG0
X
IM
SPD
LSB
R
MSB
SGN
D15
7
…
89
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2481 F04
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