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參數(shù)資料
| 型號(hào)： | DC951A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 8/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2481 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC951A Design File DC951A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2481 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2481HDD#TRPBF-ND - IC ADC DELTA SIGMA 16BIT 10DFN LTC2481HDD#PBF-ND - IC ADC 16BIT I2C 7.5SPS 10DFN LTC2481CDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481IDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481IDD#PBF-ND - IC ADC 16BIT I2C 10-DFN LTC2481CDD#PBF-ND - IC ADC 16BIT I2C 10-DFN |
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LTC2481
16
2481fc
APPLICATIONS INFORMATION
LTC2481 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2481’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NACK) by leaving
SDA HIGH. If the conversion is complete, it issues an
acknowledge (ACK) by pulling SDA LOW.
The LTC2481 has two registers. The output register contains
the result of the last conversion and a user programmable
conguration register that sets the converter operation
mode.
The output register contains the last conversion result. After
each conversion is completed, the device automatically
enters the sleep state where the supply current is reduced
to 1μA. When the LTC2481 is addressed for a Read
operation, it acknowledges (by pulling SDA LOW) and
acts as a transmitter. The master and receiver can read up
to three bytes from the LTC2481. After a complete Read
operation (3 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same input/output phase will be NACKed. The LTC2481
output data stream is 24 bits long, shifted out on the falling
edges of SCL. The rst bit is the conversion result sign bit
(SIG), see Tables 3 and 4. This bit is HIGH if VIN ≥ 0. It is
LOW if VIN <0. The second bit is the most signicant bit
(MSB) of the result. The rst two bits (SIG and MSB) can
be used to indicate over range conditions. If both bits are
HIGH, the differential input voltage is above +FS and the
following 16 bits are set to LOW to indicate an overrange
condition. If both bits are LOW, the input voltage is below
–FS and the following 16 bits are set to HIGH to indicate
an underrange condition. The function of these two bits
is summarized in Table 3. The next 16 bits contain the
conversion results in binary two’s complement format.
The remaining six bits are a readback of the conguration
register.
Table 3. LTC2481 Status Bits
INPUT RANGE
BIT 23 SIG
BIT 22 MSB
VIN ≥ 0.5 VREF
11
0V ≤ VIN < 0.5 VREF
1/0
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < – 0.5 VREF
00
As long as the voltage on the IN+ and IN– pins is main-
tained within the – 0.3V to (VCC+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF/GAIN
to +FS = 0.5 VREF/GAIN. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
input voltages below –FS, the conversion result is clamped
to the value corresponding to –FS – 1LSB.
Table 4. LTC2481 Output Data Format
DIFFERENTIAL INPUT VOLTAGE VIN*
BIT 23 SIG
BIT 22 MSB
BIT 21
BIT 20
BIT 19
…
BIT 6
VIN* ≥ FS**
1
0
…
0
FS** – 1LSB
1
0
1
…
1
0.5 FS**
1
0
1
0
…
0
0.5 FS** – 1LSB
1
0
1
…
1
0
1/0***
0
…
0
–1LSB
0
1
…
1
– 0.5 FS**
0
1
0
…
0
– 0.5 FS** – 1LSB
0
1
0
1
…
1
–FS**
0
1
0
…
0
VIN* < –FS**
0
1
…
1
* The differential input voltage VIN = IN+ – IN–.
** The full-scale voltage FS = 0.5 VREF/GAIN.
*** The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
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