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參數(shù)資料
| 型號(hào)： | DLP-HS-FPGA3 |
| 廠商： | DLP Design Inc |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大小： | 0K |
| 描述： | MODULE USB-TO-FPGA SPARTAN 3A |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FPGA |
| 模塊/板類型： | FPGA 模塊 |
| 適用于相關(guān)產(chǎn)品： | USB |
| 其它名稱： | 813-1036 |
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Rev. 1.1 (April 2012)
4
DLP Design, Inc.
The User I/O Block controls access to the 63 user I/O pins accessible through the top- and bottom-
side headers. Every one of these pins can be either an input or an output. The User I/O Block can
configure these pins as inputs and read their state, or as outputs and drive them high or low. (As a
side note, 48 of these user I/O pins can be configured as 24 differential pairs, 8 can be configured as
global clock inputs and 6 can be configured as regional clock inputs.)
The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle and the
read and write access. Read and write access is available in 4-byte bursts. The traces between the
DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at
266 Mbit/s (clocked at 133MHz). The interface creates and aligns the Data Strobes (DQS) based on
an external feedback trace that matches two times the trace length between the FPGA and the DDR2
SDRAM. The Initialization, Read and Write commands are initiated by the USB interface block and
executed by the DDR2 SDRAM interface block.
The Heartbeat Pulse Generator takes the internal system clock and divides it down so that the
onboard Heartbeat LED will be turned on and off for a duration of approximately one-half second.
The Clock Generator Block receives the 66.666-MHz clock and produces both the 133-MHz clocks
required to run the DDR2 SDRAM memory device and the 100-MHz clock for the remaining internal
logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks.
The design occupies the following FPGA resources on the DLP-HS-FPGA3 module’s XC3S1400A:
More reference designs are planned. Please contact DLP Design with any specific requests.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DLP-HS-FPGA-A | 功能描述:FPGA Embedded Module Spartan-3A, XC3S200A FT2232H 66MHz 32MB 制造商:dlp design inc. 系列:FPGA 零件狀態(tài):有效 模塊/板類型:FPGA，USB ?? 核心處理器:Spartan-3A，XC3S200A 協(xié)處理器:FT2232H 速度:66MHz 閃存大小:- RAM 容量:32Mb 連接器類型:USB - B，引腳接頭 大小/尺寸:3" x 1.2"（76.2mm x 30.5mm） 工作溫度:0°C ~ 70°C 標(biāo)準(zhǔn)包裝:1 |
| DLP-IO14 | 功能描述:數(shù)據(jù)記錄與采集 14-Channel Data-Acq Module RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| DLP-IO16 | 功能描述:界面模塊 USB/Micro Dev Board RoHS:否 制造商:4D Systems 產(chǎn)品:Serial Converters 通道/端口數(shù)量: 數(shù)據(jù)速率: 接口類型:USB, UART 工作電源電壓:3.3 V, 5 V 最大工作溫度: |
| DLP-IO20 | 功能描述:數(shù)據(jù)記錄與采集 USB-BASED 20-CHANNEL DATA ACQUISITION MOD RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| DLP-IO26 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC USB/Micro Dev Board RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評(píng)估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
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