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參數(shù)資料
| 型號： | DLP-HS-FPGA3 |
| 廠商： | DLP Design Inc |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 0K |
| 描述： | MODULE USB-TO-FPGA SPARTAN 3A |
| 標準包裝： | 1 |
| 系列： | FPGA |
| 模塊/板類型： | FPGA 模塊 |
| 適用于相關產(chǎn)品： | USB |
| 其它名稱： | 813-1036 |
Rev. 1.1 (April 2012)
6
DLP Design, Inc.
6.0 BITLOADAPP SOFTWARE
Windows software is provided for use with the DLP-HS-FPGA3 that will load an FPGA configuration
(*.bit) file directly to the SPI Flash device via the USB interface. This application (illustrated below)
will allow the user to erase the Flash, verify the erasure and then program and verify the Flash:
7.0 JTAG INTERFACE
The easiest way to load an FPGA configuration (*.bit) file to the FPGA is to run the BitLoadApp
software then select and program a file from the local hard drive directly to the SPI Flash. Once
written to the SPI Flash, the configuration will load to the FPGA and execute. Alternatively, a
traditional JTAG header location is provided on the DLP-HS-FPGA3 giving the user access to the
specific pins required by the development tools. (Refer to the schematic contained within this
datasheet for details.)
8.0 EEPROM SETUP / MPROG
The DLP-HS-FPGA3 has a dual-channel USB interface to the host PC. Channel B is used exclusively
to load an FPGA configuration (*.bit) file to the SPI Flash. This configuration data is automatically
transferred to the FPGA when power is applied to the module or when the PROG pin is driven low
and then released by the application software. Channel A is used for communication between the
FPGA and the host PC at run time. A 93LC56B EEPROM connected to the USB interface IC is used
to store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID
(VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX) and port
type (UART serial or FIFO parallel).
As mentioned above, Channel B is used exclusively for loading the FPGA’s configuration to the SPI
Flash, and Channel A is used for communication between the host PC and the DLP-HS-FPGA3. As
such, the D2XX drivers and 245 FIFO mode must be selected in the EEPROM for Channel B.
Channel A must use the 245 FIFO mode, but it can use either the VCP or D2XX drivers. The VCP
drivers make the DLP-HS-FPGA3 appear as an RS232 port to the host application. The D2XX drivers
provide faster throughput but require working with a *.lib or *.dll library in the host application.
The operational modes and other EEPROM selections are written to the EEPROM using the MPROG
utility. This utility and its manual are available for download from the bottom of the page at
www.dlpdesign.com.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DLP-HS-FPGA-A | 功能描述:FPGA Embedded Module Spartan-3A, XC3S200A FT2232H 66MHz 32MB 制造商:dlp design inc. 系列:FPGA 零件狀態(tài):有效 模塊/板類型:FPGA，USB ?? 核心處理器:Spartan-3A，XC3S200A 協(xié)處理器:FT2232H 速度:66MHz 閃存大小:- RAM 容量:32Mb 連接器類型:USB - B，引腳接頭 大小/尺寸:3" x 1.2"（76.2mm x 30.5mm） 工作溫度:0°C ~ 70°C 標準包裝:1 |
| DLP-IO14 | 功能描述:數(shù)據(jù)記錄與采集 14-Channel Data-Acq Module RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| DLP-IO16 | 功能描述:界面模塊 USB/Micro Dev Board RoHS:否 制造商:4D Systems 產(chǎn)品:Serial Converters 通道/端口數(shù)量: 數(shù)據(jù)速率: 接口類型:USB, UART 工作電源電壓:3.3 V, 5 V 最大工作溫度: |
| DLP-IO20 | 功能描述:數(shù)據(jù)記錄與采集 USB-BASED 20-CHANNEL DATA ACQUISITION MOD RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| DLP-IO26 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC USB/Micro Dev Board RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
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