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參數(shù)資料
| 型號： | DM164134 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 83/116頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV PIC18F4XK22 |
| 標準包裝： | 1 |
| 系列： | PIC® 18F |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | PIC18F4XK22，PIC18F2XK22 |
| 所含物品： | 板，文檔 |
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2006 Microchip Technology Inc.
DS41159E-page 67
PIC18FXX8
REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1
= Access program Flash memory
0
= Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EE or Configuration Select bit
1
= Access Configuration registers
0
= Access program Flash or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1
= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0
= Perform write only
bit 3
WRERR: Write Error Flag bit
1
= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0
= The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Write Enable bit
1
= Allows write cycles
0
= Inhibits write to the EEPROM or Flash memory
bit 1
WR: Write Control bit
1
= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0
= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0
= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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