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參數(shù)資料
| 型號(hào)： | DS1846E-010+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC NV TRI-POT MEM MON 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 100，256 |
| 電阻（歐姆）： | 10k，100k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 非易失 |
| 接口： | 3 線串行（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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DS1846
18 of 18
NOTES:
1) All voltages are referenced to ground.
2) I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
3) ISTBY specified with VCC = 5.0V and control port logic pins are driven to the appropriate logic levels.
Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for the
corresponding inactive state. All inputs should be connected high.
4) A fast-mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit
to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released.
5) After this period, the first clock pulse is generated.
6) The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the
SCL signal.
7) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IN
MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
8) C
B—total capacitance of one bus line in picofarads, timing referenced to (0.9 x VCC) and (0.1 x VCC).
9) EEPROM write begins after a stop condition occurs.
10) Resistor inputs can not go beneath GND by more than 0.5V or above VCC by more than 0.5V.
11) Absolute linearity is used to measure expected wiper voltage as determined by wiper position.
12) Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
positions.
13) When used as a rheostat or variable resistor the temperature coefficient applies: 750ppm/°C. When
used as a voltage-divider or potentiometer, the effective temperature coefficient approaches
30ppm/°C.
14) Valid for VCC = 5V only.
15) Valid at +25°C only.
16) Noise immunity pulses < 2
ms at VCCTP minimum do not cause a reset.
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| DS1847 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
| DS1847-010 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
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| DS1847B-010 | 功能描述:數(shù)字電位計(jì) IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1847B-010/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL NV TEMP CNTRL VAR RES 10/10K T - Tape and Reel |
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