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參數(shù)資料
| 型號： | DS1846E-010+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC NV TRI-POT MEM MON 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 100，256 |
| 電阻（歐姆）： | 10k，100k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 3 線串行（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1846
8 of 18
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
byte has been received. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the master to generate the stop condition.
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit
after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended
with a stop condition or with a repeated start condition. Since a repeated start condition is also the
beginning of the next serial transfer, the bus is not released.
The DS1846 can operate in the following two modes:
1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address recognition is performed by hardware after the
slave (device) address and direction bit has been received.
2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1846 while the serial clock is input on SCL. Start and stop conditions
are recognized as the beginning and end of a serial transfer.
3) Slave Address: Command/control byte is the first byte received following the start condition from
the master device. The command/control byte consists of a 6-bit control code. For the DS1846, this is
set as 101000 binary for read/write operations. The next bit of the command/control byte is the device
select bit or slave address (A0). It is used by the master device to select which of two devices is to be
accessed. When reading or writing the DS1846, the device-select bits must match the device-select
pin (A0). The last bit of the command/control byte (R/W) defines the operation to be performed.
When set to a ‘1’, a read operation is selected, and when set to a ‘0’, a write operation is selected.
Following the start condition, the DS1846 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the 101000 control code, the appropriate device address bit, and the
read/write bit, the slave device outputs an acknowledge signal on the SDA line.
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| DS1847E-010/T&R | IC RES TEMP-CNTRL 10/10K 14TSSOP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS1847 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
| DS1847-010 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
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| DS1847B-010 | 功能描述:數(shù)字電位計(jì) IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1847B-010/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL NV TEMP CNTRL VAR RES 10/10K T - Tape and Reel |
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