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參數(shù)資料
| 型號： | DS1846E-010+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC NV TRI-POT MEM MON 20TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 接片： | 100，256 |
| 電阻（歐姆）： | 10k，100k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標準值 750 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 3 線串行（設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1846
7 of 18
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the start and stop conditions. The DS1846 operates as a
slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the
2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications.
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data line from high to low while the clock is high
defines a start condition.
Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high
defines the stop condition.
Data Valid: The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line can be changed during
the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how
data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between start and stop conditions is not limited and is determined by the master
device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1846 works in both modes.
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| DS1847E-010/T&R | IC RES TEMP-CNTRL 10/10K 14TSSOP |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| DS1847 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
| DS1847-010 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
| DS1847-050 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Temperature-Controlled NV Variable Resistor |
| DS1847B-010 | 功能描述:數(shù)字電位計 IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1847B-010/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL NV TEMP CNTRL VAR RES 10/10K T - Tape and Reel |
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