Table 01h, Register F8h: ALARM EN3 PO" />
參數(shù)資料
型號(hào)： DS1876T+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 36/69頁(yè)
文件大小： 0K
描述： IC CTRLR SFP DUAL LDD 28TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： SFP 激光控制器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 10mA
安裝類型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TQFN-EP（5x5）
包裝： 帶卷 (TR)
41
Maxim Integrated
SFP Controller with Dual LDD Interface
DS1876
Table 01h, Register F8h: ALARM EN3
POWER-ON VALUE
00h
READ ACCESS
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS
PW2 or (PW1 and RWTBL1C)
A2h AND B2h MEMORY
Mixture of common memory locations and different memory locations (see the
descriptions below)
MEMORY TYPE
Nonvolatile (SEE)
F8h
<C>TEMP HI
<C>TEMPLO
<C>VCCHI
<C>VCC LO
<D>BMON HI
<D>BMONLO
<D>PMON HI
<D>PMONLO
BIT 7
BIT 0
Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.
BIT 7
TEMP HI [A2h or B2h]:
0 = Disables interrupt from TEMP HI alarm.
1 = Enables interrupt from TEMP HI alarm.
BIT 6
TEMP LO [A2h or B2h]:
0 = Disables interrupt from TEMP LO alarm.
1 = Enables interrupt from TEMP LO alarm.
BIT 5
VCC HI [A2h or B2h]:
0 = Disables interrupt from VCC HI alarm.
1 = Enables interrupt from VCC HI alarm.
BIT 4
VCC LO [A2h or B2h]:
0 = Disables interrupt from VCC LO alarm.
1 = Enables interrupt from VCC LO alarm.
BIT 3
BMON1 HI [A2h]:
0 = Disables interrupt from BMON1 HI alarm.
1 = Enables interrupt from BMON1 HI alarm.
BMON2 HI [B2h]:
0 = Disables interrupt from BMON2 HI alarm.
1 = Enables interrupt from BMON2 HI alarm.
BIT 2
BMON1 LO [A2h]:
0 = Disables interrupt from BMON1 LO alarm.
1 = Enables interrupt from BMON1 LO alarm.
BMON2 LO [B2h]:
0 = Disables interrupt from BMON2 LO alarm.
1 = Enables interrupt from BMON2 LO alarm.
BIT 1
PMON1 HI [A2h]:
0 = Disables interrupt from PMON1 HI alarm.
1 = Enables interrupt from PMON1 HI alarm.
PMON2 HI [B2h]:
0 = Disables interrupt from PMON2 HI alarm.
1 = Enables interrupt from PMON2 HI alarm.
BIT 0
PMON1 LO [A2h]:
0 = Disables interrupt from PMON1 LO alarm.
1 = Enables interrupt from PMON1 LO alarm.
PMON2 LO [B2h]:
0 = Disables interrupt from PMON2 LO alarm.
1 = Enables interrupt from PMON2 LO alarm.
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