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參數(shù)資料
| 型號： | DS1876T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR SFP DUAL LDD 28TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | SFP 激光控制器 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | I²C |
| 電流 - 電源： | 10mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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15
Maxim Integrated
SFP Controller with Dual LDD Interface
DS1876
The ADC results (after right-shifting, if used) are com-
pared to the alarm and warning thresholds after each
conversion, and the corresponding alarms are set that
can be used to trigger the TXFOUT output. These ADC
thresholds are user programmable, as are the masking
registers that can be used to prevent the alarms from trig-
gering the TXFOUT output.
ADC Timing
There are six analog channels that are digitized in a
round-robin fashion in the order as shown in Figure 4.
The total time required to convert all six channels is tRR
(see the Analog Voltage Monitoring Characteristics table
for details).
Right-Shifting ADC Result
If the weighting of the ADC digital reading must conform
to a predetermined full-scale (PFS) value defined by
a standard’s specification (e.g., SFF-8472), then right-
shifting can be used to adjust the PFS analog measure-
ment range while maintaining the weighting of the ADC
results. The DS1876’s range is wide enough to cover all
requirements; when the maximum input value is P 1/2
the FS value, right-shifting can be used to obtain greater
accuracy. For instance, the maximum voltage might be
1/8 the specified PFS value, so only 1/8 of the converter’s
range is effective over this range. An alternative is to cali-
brate the ADC’s full-scale range to 1/8 the readable PFS
value and use a right-shift value of 3. With this implemen-
tation, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right-shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried
out based on the contents of right-shift control registers
(Table 02h, Registers 8Eh
-8Fh) in EEPROM. Four analog
channels—PMON1, PMON2, BMON1, and BMON2—
each have 3 bits allocated to set the number of right-
shifts. Up to seven right-shift operations are allowed and
are executed as a part of every conversion before the
results are compared to the high and low alarm levels, or
loaded into their corresponding measurement registers
(Lower Memory, Registers 64h–6Bh). This is true during
the setup of internal calibration as well as during subse-
quent data conversions.
Low-Voltage Operation
The DS1876 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the sup-
ply voltage rises above POA, the outputs are disabled,
all SRAM locations are set to their defaults, shadowed
EEPROM (SEE) locations are zero, and all analog cir-
cuitry is disabled. When VCC reaches POA, the SEE is
recalled, and the analog circuitry is enabled. While VCC
remains above POA, the device is in its normal operating
state, and it responds based on its nonvolatile configu-
ration. If during operation VCC falls below POA, but is
still above POD, the SRAM retains the SEE settings from
the first SEE recall, but the device analog is shut down
and the outputs disabled. If the supply voltage recovers
back above POA, the device immediately resumes nor-
mal operation. If the supply voltage falls below POD, the
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time VCC next
exceeds POA. Figure 5 shows the sequence of events
as the voltage varies.
Any time VCC is above POD, the I2C interface can be
used to determine if VCC is below the POA level. This
is accomplished by checking the RDYB bit in the status
byte (Lower Memory, Register 6Eh). RDYB is set when
VCC is below POA; when VCC rises above POA, RDYB
is timed (within 500Fs) to go to 0, at which point the part
is fully functional.
Figure 4. ADC Round-Robin Timing
TEMP
VCC
BMON1
BMON2
PMON1
PMON2
TEMP
ONE ROUND-ROBIN ADC CYCLE
tRR
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LO
ALARM THRESHOLD. THIS ALSO OCCURS IF THERE ARE BOTH A TXD1 EVENT AND A TXD2 EVENT UNDER THE SAME CONDITIONS AS PREVIOUSLY MENTIONED.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1877 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:SFP Controller for Dual Rx Interface |
| DS1877T+ | 功能描述:ADC / DAC多通道 SFP+ Controller w/ Dual RX Interface RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| DS1877T+T&R | 制造商:Maxim Integrated Products 功能描述:SFP CTRLR FOR DUAL RX INTERFACE TQF - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC CTLR/MON SFP 1-2CH 28TQFN |
| DS1877T+T&R | 功能描述:ADC / DAC多通道 SFP+ Controller w/ Dual RX Interface RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| DS1877T+TR | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:SFP Controller for Dual Rx Interface |
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