Table 01h, Register FAh: ALARM EN" />
參數(shù)資料
型號(hào): DS1876T+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 37/69頁(yè)
文件大小: 0K
描述: IC CTRLR SFP DUAL LDD 28TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: SFP 激光控制器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 10mA
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
42
Maxim Integrated
SFP Controller with Dual LDD Interface
DS1876
Table 01h, Register F9h: RESERVED
Table 01h, Register FAh: ALARM EN1
Table 01h, Register FBh: RESERVED
POWER-ON VALUE
READ ACCESS
N/A
WRITE ACCESS
N/A
A2h AND B2h MEMORY
N/A
MEMORY TYPE
N/A
This register is reserved.
POWER-ON VALUE
00h
READ ACCESS
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS
PW2 or (PW1 and RWTBL1C)
A2h AND B2h MEMORY
Different A2h and B2h memory locations
MEMORY TYPE
Nonvolatile (SEE)
FAh
RESERVED
HBAL
RESERVED
TXP HI
TXP LO
BIT 7
BIT 0
Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see
Figure 9). The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.
BITS 7:4, 2
RESERVED
BIT 3
HBAL: Enables alarm to create internal signal FETG.
0 = Disables interrupt from HBAL alarm.
1 = Enables interrupt from HBAL alarm.
BIT 1
TXP HI: Enables alarm to create internal signal FETG.
0 = Disables interrupt from TXP HI alarm.
1 = Enables interrupt from TXP HI alarm.
BIT 0
TXP LO: Enables alarm to create internal signal FETG.
0 = Disables interrupt from TXP LO alarm.
1 = Enables interrupt from TXP LO alarm.
POWER-ON VALUE
READ ACCESS
N/A
WRITE ACCESS
N/A
A2h AND B2h MEMORY
N/A
MEMORY TYPE
N/A
This register is reserved.
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