參數(shù)資料
型號(hào): DS1876T+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 44/69頁(yè)
文件大?。?/td> 0K
描述: IC CTRLR SFP DUAL LDD 28TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: SFP 激光控制器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 10mA
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
49
Maxim Integrated
SFP Controller with Dual LDD Interface
DS1876
Table 02h, Register 8Ah: CNFGC
Table 02h, Register 8Bh: DEVICE ADDRESS
FACTORY DEFAULT
00h
READ ACCESS
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS
PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY
Common A2h and B2h memory location
MEMORY TYPE
Nonvolatile (SEE)
8Ah
TXDFG2
TXDFLT2
TXDIO2
TXDFG1
TXDFLT1
TXDIO1
RESERVED
BIT 7
BIT 0
BIT 7
TXDFG2: See Figure 9.
0 = FETG2, an internal signal, has no effect on TXDOUT2.
1 = FETG2 is enabled and ORed with other possible signals to create TXDOUT2.
BIT 6
TXDFLT2: See Figure 9.
0 = TXF2 pin has no effect on TXDOUT2.
1 = TXF2 pin is enabled and ORed with other possible signals to create TXDOUT2.
BIT 5
TXDIO2: See Figure 9.
0 = (default) TXD2 input signal is enabled and ORed with other possible signals to create TXDOUT2.
1 = TXD2 input signal has no effect on TXDOUT2.
BIT 4
TXDFG1: See Figure 9.
0 = FETG1, an internal signal, has no effect on TXDOUT1.
1 = FETG1 is enabled and ORed with other possible signals to create TXDOUT1.
BIT 3
TXDFLT1: See Figure 9.
0 = TXF1 pin has no effect on TXDOUT1.
1 = TXF1 pin is enabled and ORed with other possible signals to create TXDOUT1.
BIT 2
TXDIO1: See Figure 9.
0 = (default) TXD1 input signal is enabled and ORed with other possible signals to create TXDOUT1.
1 = TXD1 input signal has no effect on TXDOUT1.
BITS 1:0
RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS
PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY
Common A2h and B2h memory location
MEMORY TYPE
Nonvolatile (SEE)
8Bh
SEE
23
22
21
SEE
BIT 7
BIT 0
This value becomes the I2C slave address for the main memory when the ASEL bit (Table 02h, Register 88h)
is set. If A0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x
makes the main device addresses A4h and B4h.
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