參數(shù)資料
型號: DS21448DK
廠商: Maxim Integrated Products
文件頁數(shù): 17/60頁
文件大小: 0K
描述: KIT DESIGN LIU DS21448 T1/J1/E1
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS21448
已供物品: 板,子卡,CD
DS21448 3.3V T1/E1/J1 Quad Line Interface
24 of 60
The bits in the SR register have the unique ability to initiate a hardware interrupt through the
INT output pin. Each
of the alarms and events in the SR can be either masked or unmasked from the interrupt pin through the interrupt
mask register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in the SR act differently than the
interrupts caused by the other status bits in the SR. The RCL, RUA1, and LOTC bits forces the
INT pin low
whenever they change state (i.e., go active or inactive). The
INT pin is allowed to return high (if no other interrupts
are present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present.
The other status bits in the SR can force the
INT pin low when they are set. The INT pin is allowed to return high (if
no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
The host can quickly determine which of the four LIU channels is generating an interrupt by reading one of the
unused addresses in the 16h–1Fh range in any LIU channel. See the following LIU channel interrupt status
description for additional information.
LIU Channel Interrupt Status
(MSB)
(LSB)
LIU4
LIU3
LIU2
LIU1
NAME
POSITION
FUNCTION
N/A
7
Not Assigned. Could be any value when read.
N/A
6
Not Assigned. Could be any value when read.
N/A
5
Not Assigned. Could be any value when read.
N/A
4
Not Assigned. Could be any value when read.
LIU4
3
LIU4 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 4 is
asserting an interrupt.
LIU3
2
LIU3 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 3 is
asserting an interrupt.
LIU2
1
LIU2 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 2 is
asserting an interrupt.
LIU1
0
LIU1 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 1 is
asserting an interrupt.
SR (06H): Status Register
(MSB)
(LSB)
LUP
LDN
LOTC
RUA1
RCL
TCLE
TOCD
PRBSD
NAME
POSITION
FUNCTION
LUP
(Latched)
SR.7
Loop-Up Code Detected. This bit is set when the loop-up code defined in registers RUPCD1 and
RUPCD2 is being received. See Section 6.1 for details.
LDN
(Latched)
SR.6
Loop-Down Code Detected. This bit is set when the loop-down code defined in registers
RDNCD1 and RDNCD2 is being received. See Section 6.1 for details.
LOTC
(Real Time)
SR.5
Loss-of-Transmit Clock. This bit is set when the TCLK pin has not transitioned for 5
s (±2s),
forcing the LOTC pin high.
RUA1
(Latched)
SR.4
Receive Unframed All Ones. This bit is set when an unframed all-ones code is received at RRING
and RTIP (Table 5-A).
RCL
(Latched)
SR.3
Receive Carrier Loss. This bit is set when an RCL condition exists at RRING and RTIP. See
(Table 5-A) for details.
TCLE
(Real Time)
SR.2
Transmit Current-Limit Exceeded. This bit is set when the 50mA (RMS) current limiter is activated
whether or not the current limiter is enabled.
TOCD
(Real Time)
SR.1
Transmit Open-Circuit Detect. This bit is set when the device detects that the TTIP and TRING
outputs are open circuited.
PRBSD
(Real Time)
SR.0
PRBS Detect. This bit is set when the receive side detects a 2
15 - 1 (E1) or a QRSS (T1)
pseudorandom bit sequence (PRBS).
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DS21448L+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray