參數(shù)資料
型號： DS21448DK
廠商： Maxim Integrated Products
文件頁數(shù)： 38/60頁
文件大小： 0K
描述： KIT DESIGN LIU DS21448 T1/J1/E1
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS21448
已供物品： 板，子卡，CD
DS21448 3.3V T1/E1/J1 Quad Line Interface
43 of 60
8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS21448 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Table 8-A). The DS21448
contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port
(TAP) and Boundary Scan Architecture:
Test Access Port
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The TAP has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in
Section 1 for details. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE
1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 8-1. JTAG Block Diagram
8.1 JTAG TAP Controller State Machine
This section covers the operation of the TAP controller state machine. See Figure 8-2 for details on each of the
states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the
rising edge of JTCLK (Table 8-B).
Test-Logic-Reset. Upon power-up, the TAP controller is in test-logic-reset state. The instruction register contains
the IDCODE instruction. All system logic of the device operates normally.
Run-Test-Idle. The run-test-idle is used between scan operations or during specific tests. The instruction register
and test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK
moves the controller to the select-IR-scan state.
JTDI
JTMS
JTCLK
JTRST
JTDO
TEST ACCESS PORT
CONTROLLER
VDD
BOUNDRY SCAN
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
IDENTIFICATION
REGISTER
MUX
SELECT
OUTPUT ENABLE
10k
10k
10k
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21448G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448L+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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