參數(shù)資料
型號： DS21448DK
廠商： Maxim Integrated Products
文件頁數(shù)： 40/60頁
文件大?。?/td> 0K
描述： KIT DESIGN LIU DS21448 T1/J1/E1
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS21448
已供物品： 板，子卡，CD
DS21448 3.3V T1/E1/J1 Quad Line Interface
45 of 60
Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this
state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and initiates a scan
sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the
test-logic-reset state.
Capture-IR. The capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the
exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the shift-IR state.
Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK toward the serial output. The parallel register and all test registers
remain at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the exit1-IR state.
A rising edge on JTCLK with JTMS LOW keeps the controller in the shift-IR state while moving data one stage
through the instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS LOW puts the controller in the pause-IR state. If JTMS is HIGH on the
rising edge of JTCLK, the controller enters the update-IR state and terminates the scanning process.
Pause-IR. Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK
puts the controller in the exit2-IR state. The controller remains in the pause-IR state if JTMS is LOW during a rising
edge on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS HIGH puts the controller in the update-IR state. The controller loops
back to shift-IR if JTMS is LOW during a rising edge of JTCLK in this state.
Update-IR. The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current
instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the run-test-idle state. With JTMS HIGH,
the controller enters the select-DR-scan state.
8.2 Instruction Register
The instruction register contains a shift register, as well as a latched parallel output, and is 3 bits in length. When
the TAP controller enters the shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage toward the serial
output at JTDO. A rising edge on JTCLK in the exit1-IR state or the exit2-IR state with JTMS HIGH moves the
controller to the update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift
register to the instruction parallel output. Table 8-A shows the instructions supported by the DS21448 and its
respective operational binary codes.
Table 8-A. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD. This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions.
The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into
the boundary scan register through JTDI using the shift-DR state.
BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s
normal operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21448G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448L+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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