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| 型號： | DS21448DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DESIGN LIU DS21448 T1/J1/E1 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，線路接口單元（LIU） |
| 已用 IC / 零件： | DS21448 |
| 已供物品： | 板，子卡，CD |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
11 of 60
PIN
I/O
FUNCTION
BPCLK1–BPCLK4
O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is
referenced to RCLK selectable through CCR5.7 and CCR5.6.
TTIP1–TTIP4
O
TRING–TRING4
O
Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
transformer to the line. See Section 7 for details.
RPOS1–RPOS4
O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1)
of RCLK with bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ applications.
In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ) causes a
positive-going pulse synchronous with RCLK at RNEG.
RNEG1–RNEG4
O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 =
1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ
applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ)
causes a positive-going pulse synchronous with RCLK at RNEG.
RCLK1–RCLK4
O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
TPOS1–TPOS4
I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 =
1) of TCLK for data to be transmitted out onto the line.
TNEG1–TNEG4
I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 =
1) of TCLK for data to be transmitted out onto the line.
TCLK1–TCLK4
I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit
side formatter. They can be sourced internally by MCLK or RCLK. See Common Control Register
1 and Figure 1-3.
JTRST
I
JTAG Reset
JTMS
I
JTAG Mode Select
JTCLK
I
JTAG Clock
JTDI
I
JTAG Data In
JTDO
O
JTAG Data Out
VSM
I
Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.
TVDD1–TVDD4
—
3.3V, ±5% Transmitter Positive Supply
VDD1–VDD4
—
3.3V, ±5% Positive Supply
TVSS1–TVSS4
—
Transmitter Signal Ground for Transmitter Outputs
VSS1–VSS4
—
Signal Ground
Table 2-E. Hardware Interface Mode Pin Description
PIN
I/O
FUNCTION
ETS
I
E1/T1 Select
0 = E1
1 = T1
NRZE
I
NRZ Enable
0 = bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive-going pulse when the
device receives a BPV, CV, or EXZ.
SCLKE
I
Receive and Transmit Synchronization Clock Enable. SCLKE combines RSCLKE (CCR5.3) and
TSCLKE (CCR5.2).
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048MHz synchronization transmit and receive mode
DJA
I
Disable Jitter Attenuator
0 = jitter attenuator enabled
1 = jitter attenuator disabled
JAMUX
I
Jitter Attenuator Clock Mux. Controls the source for JACLK.
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK).
1 = JACLK sourced from internal PLL (2.048 MHz at MCLK).
JAS
I
Jitter Attenuator Path Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
HBE
I
Receive and Transmit HDB3/B8ZS Enable. HBE combines RHBE (CCR2.3) and THBE
(CCR2.2).
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
L0/L1/L2
I
Line Build-Out Select Bits 0,1, and 2. These pins set the transmitter build-out; see (Table 7-A
(E1) and Table 7-B (T1).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21448G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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