參數(shù)資料
型號(hào): DS2196LN+
廠商: Maxim Integrated Products
文件頁數(shù): 140/157頁
文件大小: 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 85mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2196
83 of 157
RSCD2A: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER A
(Address = 1C Hex)
RSCD2B: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER B
(Address = BC Hex)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
RSCD2.7
Receive Spare Code Definition Bit 7. A Don’t Care if a 1 to
7 bit length is selected.
C6
RSCD2.6
Receive Spare Code Definition Bit 6. A Don’t Care if a 1 to
7 bit length is selected.
C5
RSCD2.5
Receive Spare Code Definition Bit 5. A Don’t Care if a 1 to
7 bit length is selected.
C4
RSCD2.4
Receive Spare Code Definition Bit 4. A Don’t Care if a 1 to
7 bit length is selected.
C3
RSCD2.3
Receive Spare Code Definition Bit 3. A Don’t Care if a 1 to
7 bit length is selected.
C2
RSCD2.2
Receive Spare Code Definition Bit 2. A Don’t Care if a 1 to
7 bit length is selected.
C1
RSCD2.1
Receive Spare Code Definition Bit 1. A Don’t Care if a 1 to
7 bit length is selected.
C0
RSCD2.0
Receive Spare Code Definition Bit 0. A Don’t Care if a 1 to
7 bit length is selected.
13.
CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
The
RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a UART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHBLK pins will be held high during the entire corresponding channel time. See the timing in
Section 21 for an example.
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