參數(shù)資料
型號(hào): DS2196LN+
廠商: Maxim Integrated Products
文件頁數(shù): 29/157頁
文件大?。?/td> 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 85mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2196
124 of 157
20.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
20.1DESCRIPTION
The DS2196 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP,
and IDCODE. See Figure 20-1 for a block diagram. The DS2196 contains the following items, which
meet the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 20-1: BOUNDARY SCAN ARCHITECTURE
+V
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
JTDI
JTMS
JTCLK
JTRST
JTDO
+V
Test Access Port
Controller
MUX
10K
Select
Output Enable
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