參數(shù)資料
型號: DS2196LN+
廠商: Maxim Integrated Products
文件頁數(shù): 142/157頁
文件大?。?/td> 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 85mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS2196
85 of 157
14.
TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or
in other words, can be forced to stop Bit 7 Stuffing from overwriting the data in the channels.
Transparency can be invoked on a channel by channel basis by properly setting the TTR1, TTR2, and
TTR3 registers.
Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent
(or clear). If a DS0 is programmed to be clear, no Bit 7 stuffing will be performed. However, in the D4
framing mode, bit 2 will be overwritten by a zero when a Yellow Alarm is transmitted. Also the user has
the option to prevent the TTR registers from determining which channels are to have Bit 7 stuffing
performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all 24 T1 channels will have Bit 7 stuffing
performed on them regardless of how the TTR registers are programmed. Please see Figure 21-7 for
more details.
TTR1A/TTR2A/TTR3A: TRANSMIT TRANSPARENCY REGISTER FRAMER A
(Address = 39 to 3B Hex)
TTR1B/TTR2B/TTR3B: TRANSMIT TRANSPARENCY REGISTER FRAMER B
(Address = D9 to DB Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TTR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TTR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TTR3
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1-24
TTR1.0-3.7
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
1 = this DS0 channel is transparent
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