參數(shù)資料
型號: DS21FF44
廠商: Maxim Integrated Products
文件頁數(shù): 25/117頁
文件大?。?/td> 0K
描述: IC FRAMER E1 4X4 16CH 300-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT44/DS21FF44
15 of 117
3. DS21FF44 (4 X 4) PCB LAND PATTERNS
The diagram shown below is the pin pattern that is placed on the target PCB. This is the same pattern that
would be seen as viewed through the MCM from the top.
Figure 3-1. PIN PATTERN FOR TARGET PCB (4 X 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
rpos
1
rclk
1
ts
sync1
tsync
4
tclk
4
dvss
1
rsync
4
rch
blk
4
rneg
4
tneg
4
dvss
4
rser
16
test
rpos
16
rsig
16
tsig
16
ts
sync
16
tser
16
jtdof
rpos
15
B
rsync
1
rneg
1
tpos
1
tser
1
sys
clk
1
clksi
8
mclk
sys
clk
4
rclk
4
tpos
4
dvdd
4
rsync
16
rneg
16
tpos
16
tneg
16
rch
blk
16
rsync
15
rch
blk
15
tpos
15
tsig
15
C
rser
1
rch
blk
1
tneg
1
tsig
1
tclk
3
rser
3
dvdd
1
rser4
rpos
4
tsig
4
tclk
16
rclk
16
ts
sync
13
sys
clk
16
tsync
15
rser
15
rsig
15
rclk
15
tneg
15
rneg
15
D
tclk
1
dvdd
1
rsig
1
rsig
3
dvss
1
rsync
3
tser
4
rsig4
rneg
3
rclk
3
tneg
13
tsync
16
tser
13
rclk
13
rpos
13
rch
blk
13
dvdd
4
tser
15
dvss
4
ts
sync
15
E
tser
2
sys
clk
2
tsync
1
dvdd
1
sys
clk
3
rch
blk
3
tsync
3
ts
sync
4
dvss
1
jtdi
tsig
13
tpos
13
sys
clk
13
rneg
13
rsig
13
rser
13
tclk
15
rd*
cs4*
sys
clk
15
F
tsig
2
ts
sync
2
tser
3
tsync
2
tneg
3
dvdd
4
tser
14
tsync
14
tclk
14
rser
14
G
rsync
2
rsig
2
rch
blk
2
tsig
3
ts
sync
3
int*
A6
A4
A2
A0
H
rpos
2
rneg
2
rser
2
rpos
3
tclk
2
jtms
A7
A5
A3
A1
J
tneg
2
tpos
2
rclk
8
rsync
8
tpos
3
tsync
13
rsync
13
rpos
14
rsync
14
dvss
4
K
rclk
2
tclk
8
dvdd
2
dvss
2
rsig
8
tclk
13
jtrst*
tneg
14
rsig
14
rch
blk
14
L
tneg
5
tpos
5
tsig
5
ts
sync
5
tser
5
dvdd
3
D6
D4
D2
D0
M
rpos
5
rneg
5
rclk
5
sys
clk
5
tsync
8
tser
9
D7
D5
D3
D1
N
rch
blk
5
rsig
5
rsync
5
rser
8
rch
blk
8
tsync
12
rclk
12
sys
clk
14
tpos
14
rneg
14
P
rser
5
dvdd
2
rneg
8
rpos
8
tneg
8
tclk
12
mux
rsync
12
tsig
14
rclk
14
R
tclk
5
tsync
5
tpos
8
ts
sync
8
tsig
8
dvss
3
sys
clk
12
tsig
12
rpos
12
ts
sync
14
T
tser
6
sys
clk
6
tser
8
sys
clk
9
tsync
7
tclk
7
rser
7
cs1*
rclk
9
rpos
9
rsync
9
dvdd
3
tsync
9
tpos
9
ts
sync
9
rser
12
jtdot
tclk
11
tneg
12
rneg
12
U
ts
sync
6
tsig
6
dvss
2
dvss
3
rsync
7
rch
blk
7
dvdd
2
dvss
2
rneg
9
rsig
9
rser
9
sys
clk
11
tclk
9
tneg
9
tsig
9
tsync
11
rch
blk
12
tsig
11
tssync
12
rsig
12
V
rclk
6
tneg
6
rneg
6
rsig
6
rpos
7
rsig
7
rneg
7
tneg
7
tsig
7
tsig
10
rpos
10
tneg
10
rsync
10
jtclk
rsync
11
rser
11
rch
blk
11
tpos
11
dvdd
3
tpos
12
W
tpos
6
rpos
6
sys
clk
8
rser
6
tsync
6
rclk
7
tpos
7
ts
sync
10
tser
10
rclk
10
rneg
10
rch
blk
10
tsync
10
fs1
bts
tser
11
rneg
11
tneg
11
rsig
11
tser
12
Y
rch
blk
6
rsync
6
tclk
6
cs2*
sys
clk
7
tser
7
ts
sync
7
rch
blk
9
sys
clk
10
tpos
10
rsig
10
rser
10
tclk
10
fs0
cs3*
wr*
ts
sync
11
rclk
11
rpos
11
dvss
3
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