參數(shù)資料
型號: DS21FF44
廠商: Maxim Integrated Products
文件頁數(shù): 35/117頁
文件大?。?/td> 0K
描述: IC FRAMER E1 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT44/DS21FF44
24 of 117
Signal Name:
RNEG
Signal Description:
Receive Negative Data Input
Signal Type:
Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be connected together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
PARALLEL CONTROL PORT PINS
Signal Name:
INT*
Signal Description:
Interrupt
Signal Type:
Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the FDL Status Register. Active-low, open-drain output.
Signal Name:
FMS
Signal Description:
Framer Mode Select
Signal Type:
Input
Set low to select DS21Q44 feature set. Set high to select DS21Q43 emulation. FMS is connected to
ground for the DS21FF44/DS21FT44.
Signal Name:
MUX
Signal Description:
Bus Operation
Signal Type:
Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
D0 to D7 / AD0 to AD7
Signal Description:
Data Bus or Address/Data Bus
Signal Type:
Input /Output
In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as an 8-bit multiplexed address/data bus.
Signal Name:
A0 to A5, A7
Signal Description:
Address Bus
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be connected low.
Signal Name:
ALE (AS) / A6
Signal Description:
Address Latch Enable (Address Strobe) or A6
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive-going edge.
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
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