參數(shù)資料
型號: DS21FF44
廠商: Maxim Integrated Products
文件頁數(shù): 54/117頁
文件大小: 0K
描述: IC FRAMER E1 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT44/DS21FF44
41 of 117
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
(MSB)
(LSB)
RESALGN TESALGN
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
CCR5.7
Not Assigned. Should be set to zero when written
RESALGN
CCR5.6
Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after RSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align (Section
17).
TESALGN
CCR5.5
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action is taken if the
pointer separation is already greater or equal to half a frame. If
pointer separation is less than half a frame, the command will
be executed and data will be disrupted. Should be toggled after
TSYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent align (Section 17).
RCM4
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data appears in the
RDS0M register (Section 13).
RCM3
CCR5.3
Receive Channel Monitor Bit 3
RCM2
CCR5.2
Receive Channel Monitor Bit 2
RCM1
CCR5.1
Receive Channel Monitor Bit 1
RCM0
CCR5.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
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