參數(shù)資料
型號： DS21Q42T+
廠商： Maxim Integrated Products
文件頁數(shù)： 43/116頁
文件大?。?/td> 0K
描述： IC FRAMER ENHANCED T1 4X 128TQFP
標(biāo)準(zhǔn)包裝： 72
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 管件
DS21Q42
32 of 116
Framer Loopback
When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1) An unframed all 1’s code will be transmitted at TPOS and TNEG.
2) Data at RPOS and RNEG will be ignored.
3) All receive side signals will take on timing synchronous with TCLK instead of RCLK.
Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will
cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)
(LSB)
TFM
TB8ZS
TSLC96
TZSE
RFM
RB8ZS
RSLC96
RZSE
SYMBOL
POSITION
NAME AND DESCRIPTION
TFM
CCR2.7
Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
TB8ZS
CCR2.6
Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
TSLC96
CCR2.5
Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this bit to
a one in D4 framing applications. Must be set to one to source the
Fs pattern. See Section 15 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
TZSE
CCR2.4
Transmit FDL Zero Stuffer Enable. Set this bit to zero if using
the internal HDLC/BOC controller instead of the legacy support for
the FDL. See Section 15 for details.
0 = zero stuffer disabled
1 = zero stuffer enabled
RFM
CCR2.3
Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZS
CCR2.2
Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
RSLC96
CCR2.1
Receive SLC–96 Enable. Only set this bit to a one in D4/SLC–96
framing applications. See Section 15 for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
RZSE
CCR2.0
Receive FDL Zero Destuffer Enable. Set this bit to zero if using
the internal HDLC/BOC controller instead of the legacy support for
the FDL. See Section 15 for details.
0 = zero destuffer disabled
1 = zero destuffer enabled
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q42T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q42TN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43A 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad E1 Framer
DS21Q43AT 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43AT+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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