參數(shù)資料
型號(hào): DS21Q42T+
廠商: Maxim Integrated Products
文件頁數(shù): 77/116頁
文件大?。?/td> 0K
描述: IC FRAMER ENHANCED T1 4X 128TQFP
標(biāo)準(zhǔn)包裝: 72
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q42
63 of 116
Transmit a HDLC Message
1) Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register.
2) Enable either the THALF or TNF interrupt.
3) Read THIR to obtain TFULL status.
a) If TFULL = 0, then write a byte into the FIFO and skip to next step (special case occurs when the
last byte is to be written; in this case, set TEOM = 1 before writing the byte and then skip to Step
6).
b) If TFULL = 1, then skip to Step 5.
4) Repeat Step 3.
5) Wait for interrupt, skip to Step 3.
6) Disable THALF or TNF interrupt and enable TMEND interrupt.
7) Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1) Write 6-bit code into TBOC.
2) Set SBOC bit in TBOC = 1.
15.1.3 HDLC/BOC Register Description
HCR: HDLC CONTROL REGISTER (Address = 00 Hex)
(MSB)
(LSB)
RBR
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
POSITION
NAME AND DESCRIPTION
RBR
HCR.7
Receive BOC Reset. A 0 to 1 transition will reset the BOC
circuitry. Must be cleared and set again for a subsequent reset.
RHR
HCR.6
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
TFS
HCR.5
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR
HCR.4
Transmit HDLC/BOC Reset. A 0 to 1 transition will reset
both the HDLC controller and the transmit BOC circuitry.
Must be cleared and set again for a subsequent reset.
TABT
HCR.3
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
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