參數(shù)資料
型號： DS21Q42T+
廠商： Maxim Integrated Products
文件頁數(shù)： 96/116頁
文件大小： 0K
描述： IC FRAMER ENHANCED T1 4X 128TQFP
標準包裝： 72
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 管件
DS21Q42
80 of 116
19.2 TAP Controller State Machine
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.
Please see Figure 19.2 for details on each of the states described below.
TAP Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK.
Test-Logic-Reset
Upon power-up of the DS21Q42, the TAP Controller will be in the Test-Logic-Reset state. The
Instruction register will contain the IDCODE instruction. All system logic of the DS21Q42 will operate
normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
Test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge
on JTCLK moves the controller to the Select-IR
Capture-DR
Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.
Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register
selected by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state, and terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller
in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All Test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is low. A
rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.
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