參數(shù)資料
型號: DS21Q42T+
廠商: Maxim Integrated Products
文件頁數(shù): 81/116頁
文件大?。?/td> 0K
描述: IC FRAMER ENHANCED T1 4X 128TQFP
標(biāo)準(zhǔn)包裝: 72
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q42
67 of 116
RHFR: RECEIVE HDLC FIFO (Address = 05 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL
POSITION
NAME AND DESCRIPTION
HDLC7
RHFR.7
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC6
RHFR.6
HDLC Data Bit 6.
HDLC5
RHFR.5
HDLC Data Bit 5.
HDLC4
RHFR.4
HDLC Data Bit 4.
HDLC3
RHFR.3
HDLC Data Bit 3.
HDLC2
RHFR.2
HDLC Data Bit 2.
HDLC1
RHFR.1
HDLC Data Bit 1.
HDLC0
RHFR.0
HDLC Data Bit 0. LSB of a HDLC packet data byte.
THIR: TRANSMIT HDLC INFORMATION (Address = 06 Hex)
(MSB)
(LSB)
–––––TEMPTY
TFULL
UDR
SYMBOL
POSITION
NAME AND DESCRIPTION
–THIR.7
Not Assigned. Could be any value when read.
–THIR.6
Not Assigned. Could be any value when read.
–THIR.5
Not Assigned. Could be any value when read.
–THIR.4
Not Assigned. Could be any value when read.
–THIR.3
Not Assigned. Could be any value when read.
TEMPTY
THIR.2
Transmit FIFO Empty. A real–time bit that is set high when
the FIFO is empty.
TFULL
THIR.1
Transmit FIFO Full. A real–time bit that is set high when the
FIFO is full.
UDR
THIR.0
Underrun. Set when the transmit FIFO unwantedly empties out
and an abort is automatically sent.
Note: The UDR bit is latched and will be cleared when read.
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