參數(shù)資料
型號: DS21Q42T+
廠商: Maxim Integrated Products
文件頁數(shù): 73/116頁
文件大?。?/td> 0K
描述: IC FRAMER ENHANCED T1 4X 128TQFP
標準包裝: 72
控制器類型: T1 調幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q42
6 of 116
14. HDLC CONTROLLER ...................................................................................................................59
14.1. HDLC FOR DS0S ....................................................................................................................59
15. FDL/FS EXTRACTION AND INSERTION ..................................................................................60
15.1. HDLC AND BOC CONTROLLER FOR THE FDL ..............................................................60
15.1.1. General Overview ...........................................................................................................60
15.1.2. Status Register for the HDLC .........................................................................................61
15.1.3. HDLC/BOC Register Description ..................................................................................63
15.2. LEGACY FDL SUPPORT ......................................................................................................71
15.2.1. Ov_2.1.71........................................................................................................................71
15.2.2. Receive Section .............................................................................................................. 71
15.2.3. Transmit Section ............................................................................................................72
15.2.4. D4/SLC–96 OPERATION ..............................................................................................73
16. PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION .......................... 73
17. TRANSMIT TRANSPARENCY..................................................................................................... 76
18. INTERLEAVED PCM BUS OPERATION....................................................................................76
19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...........................79
19.1. DESCRIPTION ........................................................................................................................79
19.2. TAP CONTROLLER STATE MACHINE ..............................................................................80
19.3. INSTRUCTION REGISTER AND INSTRUCTIONS ...........................................................82
19.4. TEST REGISTERS ..................................................................................................................84
20. TIMING DIAGRAMS.......................................................................................................................88
21. OPERATING PARAMETERS .....................................................................................................103
22. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................116
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