參數(shù)資料
型號(hào)： DS21Q55DK
英文描述： Quad T1/E1/J1 Transceiver Design Kit Daughter Card
中文描述： 四路T1/E1/J1收發(fā)器開(kāi)發(fā)板子卡
文件頁(yè)數(shù)： 58/99頁(yè)
文件大?。?/td> 325K
代理商： DS21Q55DK
DS21Q50
Page 58 of 99
16. ELASTIC STORE OPERATION
The DS21Q50 contains a two–frame (512 bits) elastic store, for the receive direction. The elastic store is used
to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not
frequency locked) backplane clock which can be 2.048MHz for normal operation or 4.096MHz, 8.192MHz, or
16.384MHz when using the Interleave Bus Option. The elastic store contains full controlled slip capability.
If the receive elastic store is enabled (RCR.4=1), then the user must provide a 2.048MHz clock to the SYSCLK
pin. If the IBO function is enabled then a 4.096MHz, 8.192MHz or 16.384MHz clock must be provided at the
SYSCLK pin. The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR.5=1)
or having the RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5=0). If the user wishes to
obtain pulses at the frame boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur
at the multiframe boundary, then RCR1.6 must be set to one. If the elastic store is enabled, then either CAS
(RCR.7=0) or CRC4 (RCR.7=1) multiframe boundaries will be indicated via the RSYNC output. See Section
22.1 for timing details. If the 512–bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer
empties, then a full frame of data (256–bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set
to a one. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a
one.
17. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION
On the receiver, the RAF and RNAF registers will always report the data as it received in the Additional and
International bit locations. The RAF and RNAF registers are updated with the setting of the Receive Align Frame
bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF
registers. It has 250 us to retrieve the data before it is lost.
On the transmitter, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align
Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and
TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data in the Si bit
position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in
the CRC4 mode, or (3) have automatic E–bit insertion enabled. Data in the Sa bit position will be overwritten if
any of the TCR.3 to TCR.7 bits are set to one. Please see the register descriptions for TCR
Error! Reference
source not found.
for more details.
Register Name:
RAF
Register Description:
RECEIVE ALIGN FRAME REGISTER
Register Address:
28 Hex
Bit #
7
6
5
4
SYM
Si
0
0
1
3
1
2
0
1
1
0
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q55N 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Quad T1/E1/J1 Transceiver
DS21Q58 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:E1 Quad Transceiver
DS21Q58L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q58L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q58LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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